Patents by Inventor Che-Chia Wei

Che-Chia Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4920073
    Abstract: The present invention provides a method for inhibiting the oxidation of a titanium layer during the direct reaction of the titanium with exposed silicon areas of an integrated circuit. In one embodiment of the present invention, a titanium nitride layer is formed on the surface of the titanium layer in the reactor where the titanium layer is deposited. The titanium nitride layer provides an effective barrier against oxidation. Thus, the formation of titanium dioxide is inhibited. In addition, in those areas where titanium nitride local interconnect is to be formed between diffused areas, the extra thickness provided by the top titanium nitride layer adds in the integrity of the conductive layers. By conducting the silicidation in a nitride atmosphere, diffusion of the nitride from the titanium nitride layer into the titanium layer and substitution of those lost nitrogen atoms by the atmosphere occurs thus providing a blocking layer for the formation of titanium silicide shorts.
    Type: Grant
    Filed: May 11, 1989
    Date of Patent: April 24, 1990
    Assignee: Texas Instruments, Incorporated
    Inventors: Che-Chia Wei, Thomas E. Tang, James G. Bohlman, Monte A. Douglas
  • Patent number: 4890141
    Abstract: A CMOS device wherein the N-channel devices have n+ gates, and the P-channel devices have p+ gates. A TiN local interconnect system is used to connect the two types of gates, as well as providing connections to moat.
    Type: Grant
    Filed: June 29, 1988
    Date of Patent: December 26, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas E. Tang, Che-Chia Wei, Roger A. Haken, Richard A. Chapman
  • Patent number: 4788160
    Abstract: A process for forming shallow silicided junctions includes the step of sputtering a layer of titanium (28) over a moat region to cover a gate electrode (18) and a sidewall oxide (22) formed on the sidewalls of the gate electrode (18). The titanium is reacted with exposed silicon regions (24) and (26) to form silicide layers (30) and (32) and then dopant impurities are implanted into the substrate (10) prior to stripping the unreacted titanium. The unreacted titanium (36), (38), or (40) functions as a mask to both offset the implanted regions from the channel region (20) under the gate electrode (18) and also to prevent impurities from entering the substrate at regions outside the defined moat region.
    Type: Grant
    Filed: March 31, 1987
    Date of Patent: November 29, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: Robert H. Havemann, Roger A. Haken, Thomas E. Tang, Che-Chia Wei
  • Patent number: 4746219
    Abstract: A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overall, it will already be patterned according to this hardmask.
    Type: Grant
    Filed: November 12, 1986
    Date of Patent: May 24, 1988
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas C. Holloway, Thomas E. Tang, Che-Chia Wei, Roger A. Haken, David A. Bell
  • Patent number: 4690730
    Abstract: A cap oxide (or oxide/nitride) prevents silicon outdiffusion during the reaction step which forms direct-react titanium silicide.
    Type: Grant
    Filed: June 20, 1986
    Date of Patent: September 1, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas E. Tang, Che-Chia Wei, Roger A. Haken, Thomas C. Holloway, David A. Bell
  • Patent number: 4676866
    Abstract: A local interconnect system for VLSI integrated circuits. During self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a conductive titanium nitride layer is formed overall. A second titanium layer is then deposited overall and again reacted, to thicken the nitride layer without increasing the thickness of the silicide layers. This conductive layer is patterned and etched to provide local interconnects with a sheet resistance of the order to ten ohms per square, and also etch stops. Moreover, this local interconnect level permits contacts to be misaligned with the moat boundary, since the titanium nitride local interconnect layer can be overlapped from the moat up on to the field oxide to provide a bottom contact and diffusion barrier for a contact hole which is subsequently etched through the interlevel oxide. This local interconnect capability fulfills all of the functions which a buried contact capability fulfill, and fulfills other functions as well.
    Type: Grant
    Filed: March 7, 1986
    Date of Patent: June 30, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas E. Tang, Che-Chia Wei, Roger A. Haken, Thomas C. Holloway
  • Patent number: 4657628
    Abstract: A local interconnect system for VLSI integrated circuits. After titanium is deposited for self-aligned silicidation of exposed moat and gate regions in a nitrogen atmosphere, a hardmask is deposited and patterned over the titanium. When a conductive titanium nitride layer is formed overall, it will already be patterned according to this hardmask.
    Type: Grant
    Filed: March 7, 1986
    Date of Patent: April 14, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas C. Holloway, Thomas E. Tang, Che-Chia Wei, Roger A. Haken, David A. Bell