Abstract: A reverse fill pattern is used in an integrated circuit (IC) that comprises a metal layer having slots formed therein in the shape of rhombuses. The distribution of rhombic slots ensures that electrical current is evenly distributed in the conductor, even at the edge regions of the conductor. This even distribution of rhombic slots ensures that electrical current is evenly distributed at least in the central region, and in most if not all cases, across the entire region of the conductor including the edge regions. Thus, the reverse fill pattern prevents current crowding. By preventing current crowding, more stringent metal distribution targets can be met without creating or exacerbating problems associated with IR drop and EM, and without having to add any extra metal to avoid such problems.

Abstract: A reverse fill pattern is used in an integrated circuit (IC) that comprises a metal layer having slots formed therein in the shape of rhombuses. The distribution of rhombic slots ensures that electrical current is evenly distributed in the conductor, even at the edge regions of the conductor. This even distribution of rhombic slots ensures that electrical current is evenly distributed at least in the central region, and in most if not all cases, across the entire region of the conductor including the edge regions. Thus, the reverse fill pattern prevents current crowding. By preventing current crowding, more stringent metal distribution targets can be met without creating or exacerbating problems associated with IR drop and EM, and without having to add any extra metal to avoid such problems.

Abstract: Various systems and methods for limiting the effects of electrostatic discharge are disclosed. For example, a system for reducing the effects of electrostatic discharge is disclosed that includes at least two isolated pairs of potential planes. The two isolated pairs of potential planes may include, but are not limited to, a first VDD plane paired with a first VSS plane may be isolated from a second VDD plane that is paired with a second VSS plane. One circuit in the system is powered by a differential between one pair of the potential planes, and another circuit is powered by a differential between the other pair of potential planes. In addition, the system includes a transitional circuit that receives a signal output from the first of the aforementioned circuits, and provides a signal input to the second of the aforementioned circuits.

Abstract: An ESD power clamp utilizes both a transient triggering method integrated together with a voltage level detection circuit to disable a MOSFET transistor forming the ESD power clamp unless the voltage level on a relevant power supply rail is higher than a predetermined level above the normal power supply voltage. When the voltage level of the power supply rail is higher than the predetermined level (e.g., 10% higher, 25% higher, etc.), then the power surge is presumed to be an ESD pulse, and thus the ESD power clamp is enabled to turn ON and discharge the ESD power surge.