Patents by Inventor Che Choi Leung
Che Choi Leung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8310275Abstract: An IO interface circuit for use in a high voltage tolerant application is provided. The IO interface circuit includes a signal pad and at least a first parasitic bipolar transistor having an emitter adapted for connection to a voltage return of the interface circuit, a base adapted to receive a first control signal, and a collector connected directly to the signal pad in an open collector configuration. The interface circuit further includes a MOS control circuit coupled to the parasitic bipolar transistor and being operative to generate the first control signal. The IO interface circuit may further include an active pull-up circuit connected between a voltage supply of the interface circuit and the signal pad.Type: GrantFiled: March 27, 2008Date of Patent: November 13, 2012Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Che Choi Leung
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Patent number: 8039923Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.Type: GrantFiled: November 10, 2009Date of Patent: October 18, 2011Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Canzhong He, Che Choi Leung, Bruce W. McNeill
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Publication number: 20110043249Abstract: An IO interface circuit for use in a high voltage tolerant application is provided. The IO interface circuit includes a signal pad and at least a first parasitic bipolar transistor having an emitter adapted for connection to a voltage return of the interface circuit, a base adapted to receive a first control signal, and a collector connected directly to the signal pad in an open collector configuration. The interface circuit further includes a MOS control circuit coupled to the parasitic bipolar transistor and being operative to generate the first control signal. The IO interface circuit may further include an active pull-up circuit connected between a voltage supply of the interface circuit and the signal pad.Type: ApplicationFiled: March 27, 2008Publication date: February 24, 2011Inventors: Edward B. Harris, Che Choi Leung
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Publication number: 20100061036Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.Type: ApplicationFiled: November 10, 2009Publication date: March 11, 2010Inventors: Edward B. Harris, Canzhong He, Che Choi Leung, Bruce W. McNeill
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Patent number: 7635888Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.Type: GrantFiled: November 2, 2005Date of Patent: December 22, 2009Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Canzhong He, Che Choi Leung, Bruce W. McNeill
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Patent number: 7617467Abstract: Processor-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit; identifying ESD devices based at least in part on the input dataset; extracting devices and parasitic elements in at least a portion of the integrated circuit based at least in part on the input dataset; generating a file including connectivity information and dimensional characteristics for extracted devices and parasitic elements associated with at least the identified ESD devices in the integrated circuit; identifying at least one ESD test based on the identified ESD devices and on connectivity to the identified ESD devices; and performing a linear network analysis for each identified ESD test based at least in part on the file.Type: GrantFiled: December 14, 2006Date of Patent: November 10, 2009Assignee: Agere Systems Inc.Inventors: David Averill Bell, Che Choi Leung, Daniel Mark Wroge
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Publication number: 20080148199Abstract: Computer-implemented techniques for verifying ESD device connectivity in an IC include the steps of: receiving an input dataset including layout parameters corresponding to the integrated circuit; identifying ESD devices based at least in part on the input dataset; extracting devices and parasitic elements in at least a portion of the integrated circuit based at least in part on the input dataset; generating a file including connectivity information and dimensional characteristics for extracted devices and parasitic elements associated with at least ESD protection circuitry in the integrated circuit; identifying at least one ESD test based on the identified ESD devices and on connectivity to the respective ESD devices; and performing a linear network analysis for each identified ESD test based at least in part on the netlist evaluated under ESD conditions, the identified ESD devices being removed from the network analysis, the network analysis being used to ensure that current densities through respective conType: ApplicationFiled: December 14, 2006Publication date: June 19, 2008Inventors: David Averill Bell, Che Choi Leung, Daniel Mark Wroge
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Patent number: 7022581Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.Type: GrantFiled: July 8, 2004Date of Patent: April 4, 2006Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Canzhong He, Che Choi Leung, Bruce W. McNeill