Patents by Inventor Che-Chun Ou Yang

Che-Chun Ou Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device for generating a test pattern of a memory chip and method thereof
    Patent number: 8520453
    Abstract: A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outputting a first pre-input-output signal and a second pre-input-output signal according to a memory bank signal, a section signal, and the pattern enabling signal, executing an exclusive-OR logic operation on a third input-output signal and the second pattern signal to generate and output a first enabling signal, generating and outputting a first input-output signal and a second input-output signal according to the first enabling signal, the first pre-input-output signal and the second pre-input-output signal, and writing a predetermined logic voltage to each memory cell of the memory chip according to the first input-output signal and the second input-output signal.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: August 27, 2013
    Assignee: Etron Technology, Inc.
    Inventors: Shih-Hsing Wang, Chun-Ching Hsia, Che-Chun Ou Yang
  • DEVICE FOR GENERATING A TEST PATTERN OF A MEMORY CHIP AND METHOD THEREOF
    Publication number: 20120170387
    Abstract: A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outputting a first pre-input-output signal and a second pre-input-output signal according to a memory bank signal, a section signal, and the pattern enabling signal, executing an exclusive-OR logic operation on a third input-output signal and the second pattern signal to generate and output a first enabling signal, generating and outputting a first input-output signal and a second input-output signal according to the first enabling signal, the first pre-input-output signal and the second pre-input-output signal, and writing a predetermined logic voltage to each memory cell of the memory chip according to the first input-output signal and the second input-output signal.
    Type: Application
    Filed: December 14, 2011
    Publication date: July 5, 2012
    Inventors: Shih-Hsing Wang, Chun-Ching Hsia, Che-Chun Ou Yang