Patents by Inventor Che Fang

Che Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240094288
    Abstract: A circuit screening system including a target circuit under test receiving a first testing signal in a first period and a second testing signal in a second period; and a clock generating circuit providing a clock signal to the target circuit under test, the clock signal triggering the target circuit under test to receive the first testing signal in the first period and the second testing signal in the second period; the clock signal having a first profile and a second profile in the first period and the second period, respectively, and the first profile and the second profile having a phase difference.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 21, 2024
    Inventors: CHI-CHE WU, TSUNG-YANG HUNG, JIA-MING GUO, YI-NA FANG, MING-YIH WANG
  • Publication number: 20230293539
    Abstract: Described herein are phenyl triazole and aniline compounds that are MLL1-WDR5 protein-protein interaction inhibitors. Also disclosed herein are pharmaceutical compositions and methods of use for the phenyl triazole and the aniline compounds.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 21, 2023
    Inventors: Farbod SHOJAEI, Che FANG, J. Edward SEMPLE, Mireille GILLINGS
  • Patent number: 10681536
    Abstract: A method for determining an operation mode of a cellular device provides a first group cell identity obtaining step, a second group cell identity obtaining step and a group cell identity comparing step. The first group cell identity obtaining step includes configuring the cellular device to obtain at least one first group cell identity corresponding to a base station, and storing the at least one first group cell identity in a local list of the cellular device. The second group cell identity obtaining step includes configuring the cellular device to perform a scan procedure to obtain at least one second group cell identity. The group cell identity comparing step includes comparing the at least one first group cell identity with the at least one second group cell identity to determine the operation mode of the cellular device.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: June 9, 2020
    Assignee: WISTRON NEWEB CORPORATION
    Inventors: Kuo-He Ye, Che-Fang Yeh, Tien-Chu Wang
  • Publication number: 20150073613
    Abstract: A smart cloud service power outlet with surge protection, establishes communication with a cloud service platform via a wide-area-network. The smart cloud service power outlet detects power consumption result, and connects the cloud service platform via a wireless bridging device, so as to download a power supplying schedule from the cloud service platform and stores the power supplying schedule in a storage unit and then upload the power consumption result to the cloud service platform to generate a power consumption log. The power supplying schedule includes power supplying plan for plural days, and the smart cloud service power outlet enables or disables power supply of a power supplying interface. Furthermore, the smart cloud service power outlet receives a bypass signal or an external signal to perform a switching action opposite to the current power supply status.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 12, 2015
    Inventors: MAX CHIN LI, YUNG-CHE FANG, ROY YUAN SHIK TING
  • Patent number: 8736015
    Abstract: An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a dissipation device in the substrate, a second signal device in the substrate, a first electrical path between the first pickup device and the dissipation device, and a second electrical path between the first signal device and the second signal device. The dissipation device is outside of the deep n well, and the second signal device is outside of the deep n well. A highest point of the first electrical path is lower than a highest point of the second electrical path.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Jen Tsai, Chih-Fu Chang, Chih-Kang Chuang, Yee-Ren Wuang, David Yen, Yuan-Jen Liao, Shih-Che Fang, Hung-Che Hsueh, Chih Mou Huang
  • Publication number: 20130075856
    Abstract: An embodiment is an integrated circuit (IC) structure. The structure comprises a deep n well in a substrate, a first pickup device in the deep n well, a first signal device in the deep n well, a dissipation device in the substrate, a second signal device in the substrate, a first electrical path between the first pickup device and the dissipation device, and a second electrical path between the first signal device and the second signal device. The dissipation device is outside of the deep n well, and the second signal device is outside of the deep n well. A highest point of the first electrical path is lower than a highest point of the second electrical path.
    Type: Application
    Filed: September 27, 2011
    Publication date: March 28, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Jen Tsai, Chih-Fu Chang, Chih-Kang Chuang, Yee-Ren Wuang, David Yen, Yuan-Jen Liao, Shih-Che Fang, Hung-Che Hsueh, Chih Mou Huang
  • Patent number: 7178130
    Abstract: A system whereby a data flow language written in relatively high-level description is compiled to a hardware definition. The hardware definition is then used to configure data flow in a target processing system at execution time, or run time. In a preferred embodiment, the target processing system includes a Reduced-Instruction Set Computer (RISC) processor in communication with a finite state machine (FSM), shared memory, on-board memory, and other resources. The FSM is primarily used for accelerating matrix operations and is considered the target machine to be configured according to the dataflow definition. The RISC processor serves as a co-processor to an external central processing unit (CPU) that is a host processor for executing application code. Other embodiments can use aspects of the invention in any other processing architecture.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: February 13, 2007
    Assignee: NVidia Corporation
    Inventors: Dan Chuang, Che Fang, Bicheng William Wu
  • Publication number: 20060156220
    Abstract: A dynamic content assembly system, including an application and underlying database, with methods to support the creation, transformation and management of relationship information between resources and to enable dynamic assembly of content based on these relationships.
    Type: Application
    Filed: May 5, 2004
    Publication date: July 13, 2006
    Inventors: John Dreystadt, Timothy Allen, John Koenig, Curt Malouin, Ying-Che Fang, Andrew Dobrowolski
  • Publication number: 20040139428
    Abstract: A system whereby a data flow language written in relatively high-level description is compiled to a hardware definition. The hardware definition is then used to configure data flow in a target processing system at execution time, or run time. In a preferred embodiment, the target processing system includes a Reduced-Instruction Set Computer (RISC) processor in communication with a finite state machine (FSM), shared memory, on-board memory, and other resources. The FSM is primarily used for accelerating matrix operations and is considered the target machine to be configured according to the dataflow definition. The RISC processor serves as a co-processor to an external central processing unit (CPU) that is a host processor for executing application code. Other embodiments can use aspects of the invention in any other processing architecture.
    Type: Application
    Filed: January 14, 2003
    Publication date: July 15, 2004
    Applicant: QuickSilver Technology, Inc.
    Inventors: Dan Chuang, Che Fang, Bicheng William Wu