Patents by Inventor Che-Fu Chen

Che-Fu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12551934
    Abstract: The present disclosure describes a chuck-based device and a method for cleaning a semiconductor manufacturing system. The semiconductor manufacturing system can include a chamber, a chuck housed in the chamber and configured to hold a substrate, and a control device configured to control a translational displacement and a rotation of the chuck. The chuck can include a passage extending along a periphery of the chuck and dividing the chuck into an inner portion and an outer sidewall portion, and a first multiple of openings through the outer sidewall portion of the chuck and interconnected with the passage. The passage can be configured to transport a fluid. The first multiple of openings can be configured to dispense the fluid.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 17, 2026
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ian Hsieh, Che-fu Chen
  • Patent number: 12482682
    Abstract: A workstation includes: a processing chamber configured to process a workpiece; a load port configured to interface with an environment external to the workstation; a robotic arm configured to transfer the workpiece between the load port and the processing chamber; and a defect sensor configured to detect a defect along a surface of the workpiece when transferred between the load port and the processing chamber.
    Type: Grant
    Filed: June 19, 2024
    Date of Patent: November 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Hong Liu, Chien-Chih Wu, Che-Fu Chen
  • Publication number: 20250357218
    Abstract: A method includes: transferring a wafer from a factory interface through a load lock chamber to a buffer chamber; transferring the wafer from the buffer chamber to a process chamber; etching the wafer in the process chamber, to remove a material of the wafer; and after the wafer is etched, performing reflectance measurements to the wafer in the factory interface, the load lock chamber, the buffer chamber, or combination thereof, to identify if the material of the wafer is removed entirely according to a reflectance of the wafer.
    Type: Application
    Filed: July 29, 2025
    Publication date: November 20, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yan-Hong LIU, Daniel M.Y. YANG, Che-Fu CHEN
  • Publication number: 20250331264
    Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.
    Type: Application
    Filed: June 30, 2025
    Publication date: October 23, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu Ming HSIAO, Shen WANG, Kung-Shu HSU, Hong Pin LIN, Shiang-Bau WANG, Che-Fu CHEN
  • Patent number: 12444657
    Abstract: A method includes: transferring a wafer from a factory interface through a load lock chamber to a buffer chamber; transferring the wafer from the buffer chamber to a process chamber; etching the wafer in the process chamber, to remove a material of the wafer; and after the wafer is etched, performing reflectance measurements to the wafer in the factory interface, the load lock chamber, the buffer chamber, or combination thereof, to identify if the material of the wafer is removed entirely according to a reflectance of the wafer.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: October 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yan-Hong Liu, Daniel M. Y. Yang, Che-Fu Chen
  • Patent number: 12420314
    Abstract: The present disclosure describes a chuck-based device and a method for cleaning a semiconductor manufacturing system. The semiconductor manufacturing system can include a chamber, a chuck housed in the chamber and configured to hold a substrate, and a control device configured to control a translational displacement and a rotation of the chuck. The chuck can include a passage extending along a periphery of the chuck and dividing the chuck into an inner portion and an outer sidewall portion, and a first multiple of openings through the outer sidewall portion of the chuck and interconnected with the passage. The passage can be configured to transport a fluid. The first multiple of openings can be configured to dispense the fluid.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 23, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ian Hsieh, Che-fu Chen
  • Patent number: 12414347
    Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.
    Type: Grant
    Filed: May 15, 2024
    Date of Patent: September 9, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsu Ming Hsiao, Shen Wang, Kung Shu Hsu, Hong Pin Lin, Shiang-Bau Wang, Che-Fu Chen
  • Publication number: 20250069944
    Abstract: In an embodiment, a system includes: a gas distributor assembly configured to dispense gas into a chamber; and a chuck assembly configured to secure a wafer within the chamber, wherein at least one of the gas distributor assembly and the chuck assembly includes: a first portion comprising a convex protrusion, and a second portion comprising a concave opening, wherein the convex protrusion is configured to engage the concave opening.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 27, 2025
    Inventors: Bo-Ru CHEN, Yan-Hong LIU, Che-Fu CHEN
  • Patent number: 12165909
    Abstract: In an embodiment, a system includes: a gas distributor assembly configured to dispense gas into a chamber; and a chuck assembly configured to secure a wafer within the chamber, wherein at least one of the gas distributor assembly and the chuck assembly includes: a first portion comprising a convex protrusion, and a second portion comprising a concave opening, wherein the convex protrusion is configured to engage the concave opening.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Ru Chen, Yan-Hong Liu, Che-Fu Chen
  • Patent number: 12154813
    Abstract: The present disclosure describes an apparatus. The apparatus includes a chuck for placing an object thereon, a gas passage extending along a periphery of an outer sidewall of the chuck and separating the chuck into an inner portion and a sidewall portion, and a plurality of gas holes through the sidewall portion and configured to connect a gas external to the chuck to the gas passage.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ian Hsieh, Che-fu Chen, Yan-Hong Liu
  • Publication number: 20240387228
    Abstract: The present disclosure describes an apparatus. The apparatus includes a chuck for placing an object thereon, a gas passage extending along a periphery of an outer sidewall of the chuck and separating the chuck into an inner portion and a sidewall portion, and a plurality of gas holes through the sidewall portion and configured to connect a gas external to the chuck to the gas passage.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ian HSIEH, Che-fu CHEN, Yan-Hong LIU
  • Publication number: 20240371980
    Abstract: A method for making a semiconductor device includes: forming a first gate stack over a first fin; forming a first gate spacer extending along a side of the first gate stack; forming a second gate spacer over the first gate spacer; forming a third gate spacer over the second gate spacer, the third gate spacer; forming a source/drain region adjacent the third gate spacer; depositing an interlayer dielectric (ILD) over the source/drain region, the ILD including a third dielectric material; and removing at least a portion of the second gate spacer to form a void, while exposing a top surface of the ILD. The void includes a vertical portion extending between the first gate spacer and the source/drain region, and between the first gate spacer and the ILD. The void includes a horizontal portion extending beneath the source/drain region.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu Ming Hsiao, Ming-Jhe Sie, Hsiu-Hao Tsao, Hong Pin Lin, Che-fu Chen, An Chyi Wei, Yi-Jen Chen
  • Publication number: 20240339344
    Abstract: A workstation includes: a processing chamber configured to process a workpiece; a load port configured to interface with an environment external to the workstation; a robotic arm configured to transfer the workpiece between the load port and the processing chamber; and a defect sensor configured to detect a defect along a surface of the workpiece when transferred between the load port and the processing chamber.
    Type: Application
    Filed: June 19, 2024
    Publication date: October 10, 2024
    Inventors: Yan-Hong LIU, Chien-Chih WU, Che-Fu CHEN
  • Patent number: 12090503
    Abstract: A semiconductor process system includes a semiconductor process chamber having an interior volume. A pump extracts gases from the semiconductor process chamber via an outlet channel communicably coupled to the semiconductor process chamber. The system includes a plurality of fluid nozzles configured to prevent the backflow of particles from the outlet channel to interior volume by generating a fluid barrier within the outlet channel responsive to the pump ceasing to function.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Chin Wei, Che-fu Chen
  • Publication number: 20240297225
    Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.
    Type: Application
    Filed: May 15, 2024
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsu Ming HSIAO, Shen WANG, Kung-Shu HSU, Hong Pin LIN, Shiang-Bau WANG, Che-Fu CHEN
  • Patent number: 12068398
    Abstract: A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsu Ming Hsiao, Ming-Jhe Sie, Hsiu-Hao Tsao, Hong Pin Lin, Che-fu Chen, An Chyi Wei, Yi-Jen Chen
  • Patent number: 12040205
    Abstract: In an embodiment, a workstation includes: a processing chamber configured to process a workpiece; a load port configured to interface with an environment external to the workstation; a robotic arm configured to transfer the workpiece between the load port and the processing chamber; and a defect sensor configured to detect a defect along a surface of the workpiece when transferred between the load port and the processing chamber.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yan-Hong Liu, Chien-Chih Wu, Che-Fu Chen
  • Patent number: 12027594
    Abstract: In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: July 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsu Ming Hsiao, Shen Wang, Kung Shu Hsu, Hong Pin Lin, Shiang-Bau Wang, Che-Fu Chen
  • Patent number: 11837484
    Abstract: A method includes positioning an end effector at a height lower than a height of a wafer. The end effector is moved to a position under the wafer. A wafer backside property of the wafer is detected by using a sensor on the end effector. The wafer backside property is analyzed to obtain an analysis result.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hua Houng, Che-Fu Chen
  • Publication number: 20230372960
    Abstract: A semiconductor process system includes a semiconductor process chamber having an interior volume. A pump extracts gases from the semiconductor process chamber via an outlet channel communicably coupled to the semiconductor process chamber. The system includes a plurality of fluid nozzles configured to prevent the backflow of particles from the outlet channel to interior volume by generating a fluid barrier within the outlet channel responsive to the pump ceasing to function.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Inventors: Kai-Chin WEI, Che-fu CHEN