Patents by Inventor Che-Fu Liang
Che-Fu Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9893112Abstract: An optical sensor including a semiconductor substrate; a first light absorption region formed in the semiconductor substrate, the first light absorption region configured to absorb photons at a first wavelength range and to generate photo-carriers from the absorbed photons; a second light absorption region formed on the first light absorption region, the second light absorption region configured to absorb photons at a second wavelength range and to generate photo-carriers from the absorbed photons; and a sensor control signal coupled to the second light absorption region, the sensor control signal configured to provide at least a first control level and a second control level.Type: GrantFiled: August 26, 2016Date of Patent: February 13, 2018Assignee: Artilux CorporationInventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
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Publication number: 20180012918Abstract: A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including forming a germanium-silicon layer for the second group of photodiodes on a first semiconductor donor wafer; defining a first interconnect layer on the germanium-silicon layer; defining integrated circuitry for controlling pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer; bonding the first interconnect layer with the second interconnect layer; defining the pixels of an image sensor array on a second semiconductor donor wafer; defining a third interconnect layer on the image sensor array; and bonding the third interconnect layer with the germanium-silicon layer.Type: ApplicationFiled: September 22, 2017Publication date: January 11, 2018Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
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Publication number: 20180012916Abstract: An image sensor array including a carrier substrate; a first group of photodiodes coupled to the carrier substrate, where the first group of photodiodes include a first photodiode, and where the first photodiode includes a semiconductor layer configured to absorb photons at visible wavelengths and to generate photo-carriers from the absorbed photons; and a second group of photodiodes coupled to the carrier substrate, where the second group of photodiodes include a second photodiode, and where the second photodiode includes a germanium-silicon region fabricated on the semiconductor layer, the germanium-silicon region configured to absorb photons at infrared or near-infrared wavelengths and to generate photo-carriers from the absorbed photons.Type: ApplicationFiled: September 22, 2017Publication date: January 11, 2018Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
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Publication number: 20180012917Abstract: A method for fabricating an image sensor array having a first group of photodiodes for detecting light at visible wavelengths a second group of photodiodes for detecting light at infrared or near-infrared wavelengths, the method including growing a germanium-silicon layer on a semiconductor donor wafer; defining pixels of the image sensor array on the germanium-silicon layer; defining a first interconnect layer on the germanium-silicon layer, wherein the interconnect layer includes a plurality of interconnects coupled to the first group of photodiodes and the second group of photodiodes; defining integrated circuitry for controlling the pixels of the image sensor array on a semiconductor carrier wafer; defining a second interconnect layer on the semiconductor carrier wafer, wherein the second interconnect layer includes a plurality of interconnects coupled to the integrated circuitry; and bonding the first interconnect layer with the second interconnect layer.Type: ApplicationFiled: September 22, 2017Publication date: January 11, 2018Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
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Publication number: 20170214408Abstract: A loop filter has a first switched-capacitor network and a second switched-capacitor network. The first switched-capacitor network is coupled to an input node of the loop filter. The second switched-capacitor network is coupled to the input node of the loop filter. The input node of the loop filter is arranged to receive an input from a charge pump.Type: ApplicationFiled: July 31, 2015Publication date: July 27, 2017Inventor: Che-Fu Liang
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Publication number: 20170131389Abstract: An apparatus including a semiconductor substrate; an absorption layer coupled to the semiconductor substrate, the absorption layer including a photodiode region configured to absorb photons and to generate photo-carriers from the absorbed photons; one or more first switches controlled by a first control signal, the one or more first switches configured to collect at least a portion of the photo-carriers based on the first control signal; and one or more second switches controlled by a second control signal, the one or more second switches configured to collect at least a portion of the photo-carriers based on the second control signal, where the second control signal is different from the first control signal.Type: ApplicationFiled: October 31, 2016Publication date: May 11, 2017Inventors: Yun-Chung Na, Che-Fu Liang
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Publication number: 20170040362Abstract: An image sensor array including a carrier substrate; a first group of photodiodes coupled to the carrier substrate, where the first group of photodiodes include a first photodiode, and where the first photodiode includes a semiconductor layer configured to absorb photons at visible wavelengths and to generate photo-carriers from the absorbed photons; and a second group of photodiodes coupled to the carrier substrate, where the second group of photodiodes include a second photodiode, and where the second photodiode includes a germanium-silicon region fabricated on the semiconductor layer, the germanium-silicon region configured to absorb photons at infrared or near-infrared wavelengths and to generate photo-carriers from the absorbed photons.Type: ApplicationFiled: August 4, 2016Publication date: February 9, 2017Inventors: Yun-Chung Na, Szu-Lin Cheng, Shu-Lu Chen, Han-Din Liu, Hui-Wen Chen, Che-Fu Liang
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Patent number: 8653869Abstract: A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.Type: GrantFiled: September 13, 2012Date of Patent: February 18, 2014Assignee: Media Tek Singapore Pte. Ltd.Inventors: Tsung-Kai Kao, Che-Fu Liang, Michael A. Ashburn, Jr.
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Patent number: 8432198Abstract: An injection-locked phase-locked loop (ILPLL) with a self-aligned injection window is disclosed. In the ILPLL, a phase detector is provided to detect a phase difference between a pair of differential terminals of an injection-locked voltage-controlled oscillator (ILVCO) of the ILPLL. According to the detection, the phase detector generates a control signal, to align an oscillation output, generated from the pair of differential terminals of the ILVCO, with an injection pulse utilized in the ILVCO.Type: GrantFiled: September 2, 2011Date of Patent: April 30, 2013Assignee: Mediatek Inc.Inventors: Che-Fu Liang, Keng-Jan Hsiao
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Publication number: 20130099839Abstract: A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.Type: ApplicationFiled: September 13, 2012Publication date: April 25, 2013Inventors: Tsung-Kai Kao, Che-Fu Liang, Michael A. Ashburn, JR.
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Patent number: 8258830Abstract: An oscillator circuit is provided. The oscillator circuit includes a gated oscillator and a calibration circuit. The gated oscillator is arranged to generate an oscillator signal according to a control signal, and receive a gating signal to align an edge of the oscillator signal with an edge of the gating signal. The calibration circuit coupled to the gated oscillator is arranged to receive a first clock signal and a second clock signal, detect an alignment operation of the gated oscillator according to the first clock signal and a second clock signal and generate the control signal according to the detected alignment operation.Type: GrantFiled: July 30, 2009Date of Patent: September 4, 2012Assignee: Mediatek Inc.Inventors: Che-Fu Liang, Sy-Chyuan Hwu, Yu-Hsuan Tu
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Patent number: 8228126Abstract: A clock and data recovery circuit is disclosed and comprises a gated voltage-controlled oscillator (GVCO), a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop (DDFF). The GVCO receives a data signal and a reference voltage to generate first and second clock signals. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the first and second clock signals at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween. The DDFF receives the output signals from the matching circuit and the multiplexer, and outputs a recovered data signal.Type: GrantFiled: April 17, 2008Date of Patent: July 24, 2012Assignees: Mediatek Inc., National Taiwan UniversityInventors: Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
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Publication number: 20120062293Abstract: An injection-locked phase-locked loop (ILPLL) with a self-aligned injection window is disclosed. In the ILPLL, a phase detector is provided to detect a phase difference between a pair of differential terminals of an injection-locked voltage-controlled oscillator (ILVCO) of the ILPLL. According to the detection, the phase detector generates a control signal, to align an oscillation output, generated from the pair of differential terminals of the ILVCO, with an injection pulse utilized in the ILVCO.Type: ApplicationFiled: September 2, 2011Publication date: March 15, 2012Applicant: MEDIATEK INC.Inventors: Che-Fu Liang, Keng-Jan Hsaio
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Patent number: 8019022Abstract: An embodiment of a clock and data recovery circuit comprising a first clock and data recovery circuit with high bandwidth and a second clock and data recovery circuit with low bandwidth is disclosed. The first clock and data recovery circuit with high bandwidth receives a data signal and a reference signal to demux the data signal into a first signal and a second signal, wherein a second data rate X bps of the first signal and the second signal is half of a first data rate of the data signal. The second clock and data recovery circuit with low bandwidth receives and reduces jitter in the first signal and the second signal to output a first recovery signal and a second recovery signal.Type: GrantFiled: February 4, 2008Date of Patent: September 13, 2011Assignees: Mediatek Inc., National Taiwan UniversityInventors: Shen-luan Liu, Che-Fu Liang, Sy-Chyuan Hwu
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Patent number: 7940847Abstract: A frequency synthesizer for generating a plurality of frequencies of a MB-OFDM UWB system is disclosed, wherein the frequencies include first to fourteenth frequencies from low to high and any of the adjacent two frequencies differs by a basic intervallic frequency. The frequency synthesizer includes a phase locked loop generating an initial signal with a frequency equal to the second frequency, an intervallic frequency generator generating first to third intervallic frequencies from low to high and all being integers times the basic intervallic frequency and generating a forth intervallic frequency equal to the basic intervallic frequency, and first to third mixers connected in series, respectively receiving the fourth intervallic frequency, one of the first to third intervallic, and the first intervallic frequency, to respectively generate the first to third frequencies, the fourth to ninth and the thirteenth to fourteenth frequencies, and the tenth to twelfth frequencies.Type: GrantFiled: December 27, 2006Date of Patent: May 10, 2011Assignee: Industrial Technology Research InstituteInventors: Che-Fu Liang, Shen-Iuan Liu, Gin-Kou Ma, Tzu-Yi Yang
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Publication number: 20100182056Abstract: An oscillator circuit is provided. The oscillator circuit includes a gated oscillator and a calibration circuit. The gated oscillator is arranged to generate an oscillator signal according to a control signal, and receive a gating signal to align an edge of the oscillator signal with an edge of the gating signal. The calibration circuit coupled to the gated oscillator is arranged to receive a first clock signal and a second clock signal, detect an alignment operation of the gated oscillator according to the first clock signal and a second clock signal and generate the control signal according to the detected alignment operation.Type: ApplicationFiled: July 30, 2009Publication date: July 22, 2010Applicant: MEDIATEK INC.Inventors: Che-Fu Liang, Sy-Chyuan Hwu, Yu-Hsuan Tu
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Patent number: 7592847Abstract: A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay.Type: GrantFiled: September 26, 2007Date of Patent: September 22, 2009Assignee: Mediatek Inc.Inventors: Shen-luan Liu, Che-Fu Liang, Hsin-Hua Chen
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Publication number: 20080260087Abstract: A clock and data recovery circuit is disclosed and comprises a first gated voltage-controlled oscillator, a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop. The first GVCO receives a data signal and a reference voltage to generate a first clock signal and a second clock signal based on the data signal. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the frequency of the first clock signal and the second clock signal at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second clock signal or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween.Type: ApplicationFiled: April 17, 2008Publication date: October 23, 2008Applicants: MEDIATEK INC., NATIONAL TAIWAN UNIVERSITYInventors: Che-Fu Liang, Sy-Chyuan Hwu
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Publication number: 20080232524Abstract: An embodiment of a clock and data recovery circuit comprising a first clock and data recovery circuit with high bandwidth and a second clock and data recovery circuit with low bandwidth is disclosed. The first clock and data recovery circuit with high bandwidth receives a data signal and a reference signal to demux the data signal into a first signal and a second signal, wherein a second data rate X bps of the first signal and the second signal is half of a first data rate of the data signal. The second clock and data recovery circuit with low bandwidth receives and reduces jitter in the first signal and the second signal to output a first recovery signal and a second recovery signal.Type: ApplicationFiled: February 4, 2008Publication date: September 25, 2008Applicants: MEDIATEK INC., NATIONAL TAIWAN UNIVERSITYInventors: Shen-Iuan Liu, Che-Fu Liang, Sy-Chyuan Hwu
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Publication number: 20080231324Abstract: A phase frequency detector with two different delays is disclosed herein. The phase detector comprises a first D flip-flop, a second D flip-flop, a first delay unit and a second delay unit. The first D flip-flop receives a reference signal to output an up signal. The second D flip-flop receives a clock signal to output a down signal. The first delay unit delays the received signal with a first delay. The second delay unit delays the received signal with a second delay. When the reference signal synchronizes with the clock signal and the charge pump currents are calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the first delay, and when the reference signal does not synchronize with the clock signal and the charge pump currents are not calibrated, the high-level pulse widths of the up signal and the down signal are determined based on the second delay.Type: ApplicationFiled: September 26, 2007Publication date: September 25, 2008Applicants: MEDIATEK INC., NATIONAL TAIWAN UNIVERSITYInventors: Shen-Iuan Liu, Che-Fu Liang, Hsin-Hua Chen