Abstract: A transient voltage suppressor with adjustable trigger and holding voltages is provided, including a heavily doped substrate of a first conductivity type connected to a first node, a lightly doped epitaxial layer of a second conductivity type on the substrate, a first and third well region of the first conductivity type, a second well region of the second conductivity type, a first and third heavily doped region of the second conductivity type and a second heavily doped region of the first conductivity type. The heavily doped regions are commonly electrically connected to a second node, and individually disposed in the well regions. Trenches are disposed opposite in the substrate for electrical isolation. A floating base bipolar junction transistor and silicon controlled rectifier can be respectively formed under a positive and negative surged mode. Accordingly, the invention is advantageous of superior electrical performances, high layout flexibility and low area consumption.

Abstract: A bipolar junction transistor with adjustable gain is provided, including a semiconductor substrate and doped layer of a first conductivity type, a doped well region of a second conductivity type and a plurality of heavily doped regions. At least one detection circuit is provided with an input voltage and operable to generate an output voltage for a conducting layer to receive, such that current paths generated in the transistor can be determined when the input voltage varies under different operating conditions, including a normal operating mode, a positive and a negative surged operating mode. When a transient event takes place, the bipolar junction transistor is characterized by having a higher gain than it is operating in the normal mode. The proposed invention achieves in integrating the unidirectional and bidirectional electrical characteristics in the disclosed bipolar junction transistor structure by employing the detection circuit such that adjustable gain is obtained.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

Abstract: Disclosed are a signal transmission device and a quantum computer system for a qubit. The signal transmission device includes a transceiver circuit, a first sensing circuit board, a thermal insulation shell and a second sensing circuit board. The first sensing circuit board is coupled to the transceiver circuit. The thermal insulation shell separates a thermal insulation area. The second sensing circuit board is coupled to the qubit. The second sensing circuit board and the qubit are located in the thermal insulation area of the thermal insulation shell. The transceiver circuit is located outside the thermal insulation area of the thermal insulation shell. The first sensing circuit board and the second sensing circuit board perform mutual induction to produce energy changes, and the transceiver circuit transmits and receives a signal with the qubit through the mutual induction between the first sensing circuit board and the second sensing circuit board.

Abstract: A semiconductor device includes an insulating structure, a first electrical fuse element, a second electrical fuse element, a first spacer, a second spacer and an epitaxial structure. The insulating structure is disposed in a substrate. The first electrical fuse element and the second electrical fuse element are disposed at two sides of the insulating structure. Each of the first electrical fuse element and the second electrical fuse element includes a semiconductor layer disposed on the substrate and a mask layer disposed on the semiconductor layer. The first spacer partially covers a sidewall of the semiconductor layer of the first electrical fuse element adjacent to the insulating structure. The second spacer partially covers a sidewall of the semiconductor layer of the second electrical fuse element adjacent to the insulating structure. The epitaxial structure is disposed above the insulating structure and electrically connects the two semiconductor layers.

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first defining a PUF cell region on a substrate and then performing a process to form a defect on the PUF cell region. Preferably, the formation of the defect could be accomplished by forming a shallow trench isolation (STI) on the substrate, forming a gate material layer on the substrate and the STI, patterning the gate material layer to form a first gate material layer and a second gate material layer, and then forming an epitaxial layer between and connecting the first gate material layer and the second gate material layer.

Abstract: A control signal transmission device for a quantum computer is provided. The control signal transmission device includes a laser source, a digital-to-analog converter (DAC), an electro-optic modulation circuit, an optical fiber, an optic-electro demodulation circuit and a plurality of qubits. The laser source provides a light. The DAC provides a plurality of first control signals. The electro-optic modulation circuit integrates the corresponding first control signals into the light to generate an optical signal, and provides the optical signal to the optical fiber. The optic-electro demodulation circuit converts and splits the optical signal into a plurality of second control signals. The optic-electro demodulation circuit transmits the second control signals to the corresponding qubits. The qubits are controlled by the corresponding second control signals. An ambient temperature set by the optic-electro demodulation circuit and the qubits is much lower than a preset temperature value.

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Abstract: Semiconductor devices including fin-shaped isolation structures and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a fin extending from a semiconductor substrate; a shallow trench isolation (STI) region over the semiconductor substrate adjacent the fin; and a dielectric fin structure over the STI region, the dielectric fin structure extending in a direction parallel to the fin, the dielectric fin structure including a first liner layer in contact with the STI region; and a first fill material over the first liner layer, the first fill material including a seam disposed in a lower portion of the first fill material and separated from a top surface of the first fill material, a first carbon concentration in the lower portion of the first fill material being greater than a second carbon concentration in an upper portion of the first fill material.

Abstract: In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.

Abstract: An electrostatic discharge protection device includes a P-type substrate, an N-type well, a first P-type heavily-doped area, an N-type doped area, and a first N-type heavily-doped area. The N-type well is formed in the P-type substrate. The first P-type heavily-doped area is formed in the N-type well. The N-type doped area and the first N-type heavily-doped area are formed in the P-type substrate. The N-type doped area is coupled to the N-type well through an external conductive wire decoupled to the first P-type heavily-doped area. Alternatively, the P-type substrate and the N-type well are respectively replaced with an N-type substrate and a P-type well.

Abstract: A heterogeneous chip stacking device includes a substrate carrying structure, a position-limiting substrate structure, a first cover structure, a second cover structure and a chip carrying structure. The position-limiting substrate structure is detachably disposed on the substrate carrying structure. The first cover structure is detachably disposed above the position-limiting substrate structure. The second cover structure is detachably disposed on the first cover structure. The chip carrying structure is movably disposed above the substrate carrying structure. The position-limiting substrate structure has a plurality of position-limiting grooves for respectively accommodating a plurality of first chips. The first cover structure is disposed on the first chips to press the first chips, and the first cover structure has a plurality of first openings configured to respectively accommodate a plurality of second chips.

Abstract: A chip pad surface leveling device includes a signal control module, a glass carrying module and a temperature control module. The glass carrying module is configured to move a leveling glass substrate to contact a plurality of first convex pillar structures of a first chip or a plurality of second convex pillar structures of a second chip. The temperature control module is configured to apply a predetermined temperature to the first convex pillar structures or the second convex pillar structures, and the glass carrying module is configured to apply a predetermined pressure to the first convex pillar structures or the second convex pillar structures through the leveling glass substrate, thereby making a surface roughness of a bonding pad end of each first convex pillar structure or a surface roughness of a bonding pad end of each second convex pillar structure is not greater than 1 ?m.

Abstract: A heterogeneous chip stacking structure includes a first chip and a second chip. The first chip has a plurality of first convex pillar structures gradually formed outward from the first chip within a first predetermined time, and each of the first convex pillar structures has a first bonding pad portion. The second chip has a plurality of second convex pillar structures gradually formed outward from the second chip within a second predetermined time, and each of the second convex pillar structures has a second bonding pad portion. The first chip is configured to be disposed on the second chip, and the first bonding pad portions of the first convex pillar structures of the first chip and the second bonding pad portions of the second convex pillar structures of the second chip are in direct contact with each other and tightly coupled with each other, respectively.

Abstract: A control circuit for a synchronous rectification switch of a power converter is provided. The synchronous rectification switch and a transformer of the power converter are coupled to a connection node. The control circuit includes a first logic circuit, an integrating circuit, a setting comparator, a logic gate, and a second logic circuit. The first logic circuit provides a detection signal according to a detection voltage on the connection node. The integrating circuit performs an accumulation operation on the integrated voltage value based on the detection signal to generate a setting pulse. The setting comparator provides a comparison signal according to the detection voltage and a first predetermined voltage. The logic gate outputs a setting signal according to the setting pulse and the comparison signal. The second logic circuit continuously provides a turn-on control signal in response to the setting signal. The synchronous rectification switch is turned on in response to the turn-on control signal.

Abstract: A synchronous rectifier device for a power converter is provided. A power converter includes at least one secondary circuit and a transformer. The synchronous rectifier device includes a synchronous rectification circuit and a controller. The synchronous rectification circuit includes a synchronous rectification switch and a current receiving circuit. The synchronous rectification switch is coupled between the secondary circuit and a secondary winding of the transformer. The current receiving circuit provides a current signal based on a current flowing through the synchronous rectification switch. The controller controls the synchronous rectification switch according to the current signal. In a case that the synchronous rectification switch is turned off, when the current signal indicates that a current value of the current is greater than a predetermined value, the controller turns on the synchronous rectification switch.

Abstract: A heterogeneous chip stacking method includes providing a first chip, in which the first chip has a plurality of first convex pillar structures, and each first convex pillar structure has a first bonding pad portion; providing a second chip different from the first chip, in which the second chip has a plurality of second convex pillar structures, and each second convex pillar structures having a second bonding pad portion; placing the first chip on the second chip, in which the first bonding pad portions of the first convex pillar structures and the second bonding pad portions of the second convex pillar structures are in direct contact with each other respectively; and then applying at least one of a predetermined pressure, a predetermined temperature, and a predetermined ultrasonic frequency to tightly couple the first bonding pad portions and the second bonding pad portions with each other respectively.

Abstract: A diode test module and method applicable to the diode test module are provided. A substrate having first conductivity type and an epitaxial layer having second conductivity type on the substrate are formed. A well region having first conductivity type is formed in the epitaxial layer. A first and second heavily doped region having second conductivity type are theoretically formed in the well and connected to a first and second I/O terminal, respectively. Isolation trench is formed there in between for electrical isolation. A monitor cell comprising a third and fourth heavily doped region is provided in a current conduction path between the first and second I/O terminal when inputting an operation voltage. By employing the monitor cell, the invention achieves to determine if the well region is missing by measuring whether a leakage current is generated without additional testing equipment and time for conventional capacitance measurements.