Patents by Inventor Che Hua Chang
Che Hua Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240099154Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: UNITED MICROELECTRONICS CORPInventors: Hui-Lin Wang, Si-Han Tsai, Dong-Ming Wu, Chen-Yi Weng, Ching-Hua Hsu, Ju-Chun Fan, Yi-Yu Lin, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang
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Publication number: 20240071825Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Tin-Hao Kuo, Che-Wei Hsu
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Patent number: 11917923Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.Type: GrantFiled: April 28, 2021Date of Patent: February 27, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Ching-Hua Hsu, Si-Han Tsai, Shun-Yu Huang, Chen-Yi Weng, Ju-Chun Fan, Che-Wei Chang, Yi-Yu Lin, Po-Kai Hsu, Jing-Yin Jhang, Ya-Jyuan Hung
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Publication number: 20240055361Abstract: A method for forming alignment keys of a semiconductor structure includes: forming an oxide pad layer and a passivation layer on a substrate; forming a patterned photoresist layer on the passivation layer, and using the patterned photoresist layer as a mask to remove part of the oxide pad layer and passivation layer and expose the substrate surface in the medium voltage and alignment mark regions; forming oxide portions on the exposed substrate surface, and the oxide portions extending into the first depth of the substrate; forming deep doped wells in the low voltage and medium voltage regions; thinning the oxide portions; forming high-voltage doped wells in the high voltage and alignment mark regions; performing an etching process on the high voltage and alignment mark regions to form a second trench, as an alignment key, having a second depth greater than the first depth in the alignment mark region.Type: ApplicationFiled: September 26, 2022Publication date: February 15, 2024Inventors: TSUNG-YU YANG, Shin-Hung Li, Shan-shi Huang, Ruei Jhe Tsao, Che-Hua Chang, YUAN YU CHUNG
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Publication number: 20230197843Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first drift region, a first source/drain region, and a gate oxide layer. The gate structure and the gate oxide layer are disposed on the semiconductor substrate. The first drift region is disposed in the semiconductor substrate. The first source/drain region is disposed in the first drift region. At least a part of a first portion of the gate oxide layer is disposed between the gate structure and the semiconductor substrate in a vertical direction. A second portion of the gate oxide layer is disposed between the first portion and the first source/drain region in a horizontal direction. The second portion includes a bottom extending downwards and a first concave top surface located above the bottom. A part of the first drift region is located under the first portion and the second portion of the gate oxide layer.Type: ApplicationFiled: January 18, 2022Publication date: June 22, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tsung-Yu Yang, Shin-Hung Li, Ruei-Jhe Tsao, Che-Hua Chang
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Publication number: 20230187547Abstract: A semiconductor device includes a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate. At least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction. A thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer.Type: ApplicationFiled: January 6, 2022Publication date: June 15, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Che-Hua Chang, Shin-Hung Li, Tsung-Yu Yang, Ruei-Jhe Tsao
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Publication number: 20220216308Abstract: The present disclosure provides a high voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distance between the top surface of an electrode of the first electrode structure and the top surface of the substrate includes a first height and a second height which are different from each other.Type: ApplicationFiled: January 4, 2021Publication date: July 7, 2022Inventors: Chung-Ren Lao, Kuan-I Ho, Kuo-Chien Hsu, Che-Hua Chang, Hsiao-Ying Yang, Chih-Cherng Liao
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Patent number: 11374096Abstract: The present disclosure provides a high voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distance between the top surface of an electrode of the first electrode structure and the top surface of the substrate includes a first height and a second height which are different from each other.Type: GrantFiled: January 4, 2021Date of Patent: June 28, 2022Assignee: Vanguard International Semiconductor CorporationInventors: Chung-Ren Lao, Kuan-I Ho, Kuo-Chien Hsu, Che-Hua Chang, Hsiao-Ying Yang, Chih-Cherng Liao
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Patent number: 9211630Abstract: A grinding machine control method and a control system employing the method is disclosed. The grinding machine control method includes the step of providing a plurality of sub processing procedures each dominating a grinding machine to execute a respective processing step, the step of providing a processing scheduling processing to link the sub processing procedures into a main processing procedure, and the step of executing the main processing procedure to enable the grinding machine to run subject to the processing steps executed by the respective sub processing procedures.Type: GrantFiled: April 26, 2012Date of Patent: December 15, 2015Assignee: FALCON MACHINE TOOLS CO., LTD.Inventors: Che-Hua Chang, Cheng-Chia Wu
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Patent number: 8803234Abstract: A high voltage (HV) semiconductor device includes: a semiconductor substrate having a first conductivity type; a gate structure disposed over a portion of the semiconductor substrate; a pair of spacers respectively disposed over a sidewall of the gate structure, wherein one of the spacers is a composite spacer comprising a first insulating spacer contacting the gate structure, a dummy gate structure, and a second insulating spacer; a first drift region disposed in a portion of the semiconductor, underlying a portion of the gate structure and one of the pair of spacers, having a second conductivity type opposite to the first conductivity type; and a pair of doping regions, respectively disposed in a portion of the semiconductor substrate on opposite sides of the gate structure, wherein the pair of doping regions include the second conductivity type and one of the doping regions is disposed in the first drift region.Type: GrantFiled: March 18, 2013Date of Patent: August 12, 2014Assignee: Vanguard International Semiconductor CorporationInventors: Chih-Cherng Liao, Yun-Chou Wei, Pi-Kuang Chuang, Ching-Yi Hsu, Chih-Wei Lin, Wen-Chung Chen, Che-Hua Chang, Yung-Lung Chou, Chung-Te Chou, Cheng-Lun Cho, Ya-Han Liang
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Publication number: 20130237127Abstract: A grinding machine control method and a control system employing the method is disclosed. The grinding machine control method includes the step of providing a plurality of sub processing procedures each dominating a grinding machine to execute a respective processing step, the step of providing a processing scheduling processing to link the sub processing procedures into a main processing procedure, and the step of executing the main processing procedure to enable the grinding machine to run subject to the processing steps executed by the respective sub processing procedures.Type: ApplicationFiled: April 26, 2012Publication date: September 12, 2013Inventors: Che-Hua CHANG, Cheng-Chia WU
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Publication number: 20090080150Abstract: This invention relates to a heat dissipation device for portable computer. The heat dissipation device comprises: a housing including at least one fan casing and at least one duct, said fan casing having an air suction opening which communicates with said duct, at least one air outlet communicating with said fan casing being provided at the front end of said housing, at least one air inlet communicating with said fan casing being provided at the rear end of said housing; and at least one side-blow fan provided within the fan casing, the air suction face of the side-blow fan being opposite to the air suction opening, the air introducing from the air inlet into the duct passes being sucked by the side-blow fan into the fan casing after passing through the air suction opening and blowing out through the air outlet. In this manner, excellent heat dissipation effect collocating with the use of a portable computer can be obtained. In addition, noise generation is effectively prevented.Type: ApplicationFiled: December 28, 2007Publication date: March 26, 2009Inventors: Che Hua Chang, Ting Hui Huang, Chih Cheng Hsu