Patents by Inventor Che-Hua Hsu

Che-Hua Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11404316
    Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Tin-Hao Kuo, Che-Wei Hsu
  • Publication number: 20220216308
    Abstract: The present disclosure provides a high voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distance between the top surface of an electrode of the first electrode structure and the top surface of the substrate includes a first height and a second height which are different from each other.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 7, 2022
    Inventors: Chung-Ren Lao, Kuan-I Ho, Kuo-Chien Hsu, Che-Hua Chang, Hsiao-Ying Yang, Chih-Cherng Liao
  • Patent number: 11374096
    Abstract: The present disclosure provides a high voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distance between the top surface of an electrode of the first electrode structure and the top surface of the substrate includes a first height and a second height which are different from each other.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: June 28, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chung-Ren Lao, Kuan-I Ho, Kuo-Chien Hsu, Che-Hua Chang, Hsiao-Ying Yang, Chih-Cherng Liao
  • Patent number: 9490342
    Abstract: A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: November 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yi-Wen Chen, Zhi-Cheng Lee, Tong-Jyun Huang, Che-Hua Hsu, Kun-Hsien Lin, Tzung-Ying Lee, Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin
  • Patent number: 9384962
    Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
  • Patent number: 9034102
    Abstract: A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: May 19, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yao-Tsung Huang, Chien-Ting Lin, Che-Hua Hsu, Guang-Hwa Ma
  • Patent number: 8951855
    Abstract: A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: February 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Ming Lai, Rai-Min Huang, Tong-Jyun Huang, Che-Hua Hsu, Yi-Wen Chen
  • Publication number: 20140339652
    Abstract: A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
  • Patent number: 8816439
    Abstract: A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: August 26, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Tian-Fu Chiang, Cheng-Hsien Chou, Chien-Ming Lai, Yi-Wen Chen, Chien-Ting Lin, Guang-Hwa Ma
  • Patent number: 8802524
    Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yi-Wei Chen, Hsin-Fu Huang, Tzung-Ying Lee, Min-Chuan Tsai, Chan-Lon Yang, Chun-Yuan Wu, Teng-Chun Tsai, Guang-Yaw Hwang, Chia-Lin Hsu, Jie-Ning Yang, Cheng-Guo Chen, Jung-Tsung Tseng, Zhi-Cheng Lee, Hung-Ling Shih, Po-Cheng Huang, Yi-Wen Chen, Che-Hua Hsu
  • Patent number: 8685811
    Abstract: A method for manufacturing a CMOS device includes providing a substrate having a first active region and a second active region defined thereon, forming a first conductive type transistor and a second conductive type transistor respectively in the first and the second active regions, performing a salicide process, forming an ILD layer, performing a first etching process to remove a first gate of the first conductive type transistor and to form an opening while a high-K gate dielectric layer is exposed in a bottom of the opening, and forming at least a first metal layer in the opening.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: April 1, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Ting Lin, Li-Wei Cheng, Che-Hua Hsu, Guang-Hwa Ma, Chin-Sheng Yang
  • Publication number: 20130280900
    Abstract: A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed.
    Type: Application
    Filed: April 24, 2012
    Publication date: October 24, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Rai-Min Huang, Tong-Jyun Huang, Che-Hua Hsu, Yi-Wen Chen
  • Patent number: 8492259
    Abstract: A method of forming metal gate structure includes providing a substrate; forming a gate dielectric layer, a material layer and a polysilicon layer stacked on the substrate; forming a first mask layer, a second mask layer and a patterned photoresist on the polysilicon layer; removing portions of the second mask layer and the first mask layer to form a hard mask by utilizing the patterned photoresist as an etching mask; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the material layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: July 23, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen
  • Patent number: 8486842
    Abstract: A method of selectively removing a patterned hard mask is described. A substrate with a patterned target layer thereon is provided, wherein the patterned target layer includes a first target pattern and at least one second target pattern, and the patterned hard mask includes a first mask pattern on the first target pattern and a second mask pattern on the at least one second target pattern. A first photoresist layer is formed covering the first mask pattern. The sidewall of the at least one second target pattern is covered by a second photoresist layer. The second mask pattern is removed using the first photoresist layer and the second photoresist layer as a mask.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: July 16, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Che-Hua Hsu, Shao-Hua Hsu, Zhi-Cheng Lee, Cheng-Guo Chen
  • Patent number: 8404535
    Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: March 26, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Hao Yu, Li-Wei Cheng, Che-Hua Hsu, Cheng-Hsien Chou, Tian-Fu Chiang, Chien-Ming Lai, Yi-Wen Chen, Jung-Tsung Tseng, Chien-Ting Lin, Guang-Hwa Ma
  • Patent number: 8349682
    Abstract: An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: January 8, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
  • Publication number: 20120322218
    Abstract: A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming LAI, Yi-Wen Chen, Zhi-Cheng Lee, Tong-Jyun Huang, Che-Hua Hsu, Kun-Hsien Lin, Tzung-Ying Lee, Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin
  • Publication number: 20120309185
    Abstract: A method of forming metal gate structure includes providing a substrate; forming a gate dielectric layer, a material layer and a polysilicon layer stacked on the substrate; forming a first mask layer, a second mask layer and a patterned photoresist on the polysilicon layer; removing portions of the second mask layer and the first mask layer to form a hard mask by utilizing the patterned photoresist as an etching mask; removing the patterned photoresist, and next utilizing the hard mask as an etching mask to remove parts of the polysilicon layer and parts of the material layer. Thus, a gate stack is formed. Since the patterned photoresist is removed before forming the gate stack, the gate stack is protected from damages of the photoresist-removing process. The photoresist-removing process does not attack the sidewalls of the gate stack, so a bird's beak effect of the gate dielectric layer is prevent.
    Type: Application
    Filed: August 16, 2012
    Publication date: December 6, 2012
    Inventors: Che-Hua HSU, Shao-Hua HSU, Zhi-Cheng LEE, Cheng-Guo CHEN
  • Publication number: 20120256276
    Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 11, 2012
    Inventors: Guang-Yaw Hwang, Chun-Hsien Lin, Hung-Ling Shih, Jiunn-Hsiung Liao, Zhi-Cheng Lee, Shao-Hua Hsu, Yi-Wen Chen, Cheng-Guo Chen, Jung-Tsung Tseng, Chien-Ting Lin, Tong-Jyun Huang, Jie-Ning Yang, Tsung-Lung Tsai, Po-Jui Liao, Chien-Ming Lai, Ying-Tsung Chen, Cheng-Yu Ma, Wen-Han Hung, Che-Hua Hsu
  • Publication number: 20120244669
    Abstract: The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.
    Type: Application
    Filed: March 22, 2011
    Publication date: September 27, 2012
    Inventors: Po-Jui Liao, Tsung-Lung Tsai, Chien-Ting Lin, Shao-Hua Hsu, Yi-Wei Chen, Hsin-Fu Huang, Tzung-Ying Lee, Min-Chuan Tsai, Chan-Lon Yang, Chun-Yuan Wu, Teng-Chun Tsai, Guang-Yaw Hwang, Chia-Lin Hsu, Jie-Ning Yang, Cheng-Guo Chen, Jung-Tsung Tseng, Zhi-Cheng Lee, Hung-Ling Shih, Po-Cheng Huang, Yi-Wen Chen, Che-Hua Hsu