Patents by Inventor Che-Huai Hung

Che-Huai Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Publication number: 20100052036
    Abstract: A semiconductor device disposed on a substrate is provided. The semiconductor device includes two isolation structures, a first conductive layer, a charge trapping layer, a second conductive layer and a gate dielectric layer. The two isolation structures are disposed in the substrate to define an active area. The second conductive layer across the two isolation structures is disposed on the substrate. The first conductive layer is disposed between the two isolation structures and between the second conductive layer and the substrate. The second conductive layer electrically connects with the first conductive layer. The charge trapping layer is disposed on the substrate. The gate dielectric layer is disposed between the first conductive layer and the substrate. An interface between the two isolation structures and the first conductive layer is covered by the charge trapping layer to restrain the kink effect.
    Type: Application
    Filed: August 20, 2009
    Publication date: March 4, 2010
    Applicant: POWERCHIP SEMICONDUCTOR CORP.
    Inventors: Cheng-Hong Lee, Chih-Ming Chao, Hann-Ping Hwang, Che-Huai Hung
  • Publication number: 20070048937
    Abstract: A method of fabricating a non-volatile memory is provided. A substrate having a memory cell area and a peripheral circuit area is provided. A plurality of device isolation structures is formed in the substrate. A tunneling dielectric layer is formed on the substrate in the memory cell area and a gate oxide layer is formed on the substrate in the peripheral circuit area. A first conductive layer is formed on the substrate to cover the memory cell area and the peripheral circuit area. The first conductive layer in the memory cell area is patterned. A composite dielectric layer is formed on the substrate. The composite dielectric layer in the peripheral circuit area is removed. A second conductive layer is formed on the substrate to cover the memory cell area and the peripheral circuit area.
    Type: Application
    Filed: December 19, 2005
    Publication date: March 1, 2007
    Inventors: Chin-Chung Wang, Chia-Ping Lai, Che-Huai Hung