Patents by Inventor Che-Hung KUO
Che-Hung KUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220223512Abstract: A semiconductor package structure includes a frontside redistribution layer, a first semiconductor die, a first capacitor, a conductive terminal, and a backside redistribution layer. The first semiconductor die is disposed over the frontside redistribution layer. The first capacitor is disposed over the frontside redistribution layer and electrically coupled to the first semiconductor die. The conductive terminal is disposed below the frontside redistribution layer and electrically coupled to the frontside redistribution layer. The backside redistribution layer is disposed over the first semiconductor die.Type: ApplicationFiled: December 9, 2021Publication date: July 14, 2022Inventors: Che-Hung KUO, Hsing-Chih LIU, Tai-Yu CHEN
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Publication number: 20220130814Abstract: A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region.Type: ApplicationFiled: October 6, 2021Publication date: April 28, 2022Applicant: MEDIATEK INC.Inventors: Che-Hung Kuo, Yi-Jyun Lee
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Publication number: 20220013441Abstract: A semiconductor package structure includes a frontside redistribution layer, a stacking structure, a backside redistribution layer, a first intellectual property (IP) core, and a second IP core. The stacking structure is disposed over the frontside redistribution layer and comprises a first semiconductor die and a second semiconductor die over the first semiconductor die. The backside redistribution layer is disposed over the stacking structure. The first IP core is disposed in the stacking structure and is electrically coupled to the frontside redistribution layer through a first routing channel. The second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is separated from the first routing channel and electrically insulated from the frontside redistribution layer.Type: ApplicationFiled: June 30, 2021Publication date: January 13, 2022Inventors: Hsing-Chih LIU, Zheng ZENG, Che-Hung KUO
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Publication number: 20210351124Abstract: An interconnect structure for a redistribution layer includes an intermediate via land pad; a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad; and an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad. The array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad. The array of lower conductive vias arranged within the horseshoe-shaped via array region does not overlap with the cluster of upper conductive vias.Type: ApplicationFiled: February 18, 2021Publication date: November 11, 2021Inventors: Che-Hung Kuo, Hsing-Chih Liu
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Publication number: 20210193540Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.Type: ApplicationFiled: March 3, 2021Publication date: June 24, 2021Applicant: MediaTek Inc.Inventors: Nan-Cheng Chen, Che-Ya Chou, Hsing-Chih Liu, Che-Hung Kuo
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Publication number: 20210036405Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.Type: ApplicationFiled: October 20, 2020Publication date: February 4, 2021Applicant: MediaTek Inc.Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
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Patent number: 10847869Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.Type: GrantFiled: May 9, 2018Date of Patent: November 24, 2020Assignee: MediaTek Inc.Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen, Min-Chen Lin, Hsing-Chih Liu
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Patent number: 10636773Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor die including a first active surface and a first non-active surface. The semiconductor package structure also includes a second semiconductor die including a second active surface and a second non-active surface. The second semiconductor die is stacked on the first semiconductor die. The first non-active surface faces the second non-active surface. The semiconductor package structure further includes a first redistribution layer (RDL) structure. The first active surface faces the first RDL structure. In addition, the semiconductor package structure includes a second RDL structure. The second active surface faces the second RDL structure.Type: GrantFiled: July 6, 2016Date of Patent: April 28, 2020Assignee: MediaTek Inc.Inventors: Che-Hung Kuo, Che-Ya Chou
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Patent number: 10497678Abstract: A semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.Type: GrantFiled: October 6, 2017Date of Patent: December 3, 2019Assignee: MediaTek Inc.Inventors: Che-Hung Kuo, Ying-Chih Chen, Che-Ya Chou
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Patent number: 10468341Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.Type: GrantFiled: December 26, 2018Date of Patent: November 5, 2019Assignee: MEDIATEK INC.Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Che-Hung Kuo, Che-Ya Chou, Wei-Che Huang
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Publication number: 20190131233Abstract: A semiconductor package assembly includes a redistribution layer (RDL) structure, which RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace, and the RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The RDL structure includes a first region for a semiconductor die to be disposed thereon and a second region surrounding the first region, and the extended wing portion of the RDL contact pad is offset from a center of the first region.Type: ApplicationFiled: December 26, 2018Publication date: May 2, 2019Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Che-Hung KUO, Che-Ya CHOU, Wei-Che HUANG
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Patent number: 10199318Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.Type: GrantFiled: April 7, 2017Date of Patent: February 5, 2019Assignee: MEDIATEK INC.Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Che-Hung Kuo, Che-Ya Chou, Wei-Che Huang
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Publication number: 20180358685Abstract: One embodiment of the present disclosure provides a semiconductor package including a bottom chip package having a first side and a second side opposing the first side, and a top antenna package mounted on the first side of the bottom chip package. The bottom chip package further includes a semiconductor chip. The semiconductor chip may include a RFIC chip. The top antenna package has at least one radiative antenna element.Type: ApplicationFiled: May 9, 2018Publication date: December 13, 2018Inventors: Fu-Yi Han, Che-Ya Chou, Che-Hung Kuo, Wen-Chou Wu, Nan-Cheng Chen
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Publication number: 20180102298Abstract: A semiconductor device includes a substrate, a body structure and an electronic component. The body structure is disposed above the substrate and includes a semiconductor die, a molding compound, a conductive component and a lower redistribution layer (RDL). The semiconductor die has an active surface. The molding compound encapsulates the semiconductor die and has a lower surface, an upper surface opposite to the lower surface and a through hole extending to the upper surface from the lower surface. The conductive component is formed within the through hole. The lower RDL is formed on the lower surface of the molding compound, the active surface of the semiconductor die and the conductive component exposed from the lower surface. The electronic component is disposed above the upper surface of the molding compound and electrically connected to the lower RDL through the conductive component.Type: ApplicationFiled: October 2, 2017Publication date: April 12, 2018Inventors: Nan-Cheng Chen, Che-Ya Chou, Hsing-Chih Liu, Che-Hung Kuo
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Publication number: 20180053665Abstract: A pre-bumped redistribution layer (RDL) structure is disclosed. The pre-bumped RDL structure includes at least a dielectric layer, a first metal layer on the first surface, a second metal layer on the second surface, and a via layer electrically connecting the first metal layer and the second metal layer. At least a bump pad is formed in the first metal layer. A bump is disposed on the bump pad. The bump comprises a copper layer with its lower end directly jointed to a top surface of the bump pad.Type: ApplicationFiled: June 14, 2017Publication date: February 22, 2018Inventors: Che-Hung Kuo, Che-Ya Chou, Nan-Cheng Chen
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Publication number: 20180033774Abstract: A semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.Type: ApplicationFiled: October 6, 2017Publication date: February 1, 2018Inventors: Che-Hung KUO, Ying-Chih CHEN, Che-Ya CHOU
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Publication number: 20170338175Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure. The RDL structure includes a conductive trace. A redistribution layer (RDL) contact pad is electrically coupled to the conductive trace. The RDL contact pad is composed of a symmetrical portion and an extended wing portion connected to the symmetrical portion. The extended wing portion overlaps at least one-half of a boundary of the symmetrical portion when observed from a plan view.Type: ApplicationFiled: April 7, 2017Publication date: November 23, 2017Inventors: Nai-Wei LIU, Tzu-Hung LIN, I-Hsuan PENG, Che-Hung KUO, Che-Ya CHOU, Wei-Che HUANG
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Patent number: 9818727Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.Type: GrantFiled: February 1, 2016Date of Patent: November 14, 2017Assignee: MEDIATEK INC.Inventors: Che-Hung Kuo, Ying-Chih Chen, Che-Ya Chou
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Publication number: 20170084589Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor die including a first active surface and a first non-active surface. The semiconductor package structure also includes a second semiconductor die including a second active surface and a second non-active surface. The second semiconductor die is stacked on the first semiconductor die. The first non-active surface faces the second non-active surface. The semiconductor package structure further includes a first redistribution layer (RDL) structure. The first active surface faces the first RDL structure. In addition, the semiconductor package structure includes a second RDL structure. The second active surface faces the second RDL structure.Type: ApplicationFiled: July 6, 2016Publication date: March 23, 2017Inventors: Che-Hung KUO, Che-Ya CHOU
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Publication number: 20160268233Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.Type: ApplicationFiled: February 1, 2016Publication date: September 15, 2016Inventors: Che-Hung KUO, Ying-Chih CHEN, Che-Ya CHOU