Abstract: A semiconductor package structure includes a frontside redistribution layer, a first semiconductor die, a first capacitor, a conductive terminal, and a backside redistribution layer. The first semiconductor die is disposed over the frontside redistribution layer. The first capacitor is disposed over the frontside redistribution layer and electrically coupled to the first semiconductor die. The conductive terminal is disposed below the frontside redistribution layer and electrically coupled to the frontside redistribution layer. The backside redistribution layer is disposed over the first semiconductor die.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: An apparatus for manufacturing a semiconductor device may include a chamber, a chuck provided in the chamber, and a biased power supply physically connected with the chuck. The apparatus may include a target component provided over the chuck and the biased power supply, and a magnetron assembly provided over the target component. The magnetron assembly may include a plurality of outer magnetrons and a plurality of inner magnetrons, and a spacing between each adjacent magnetrons of the plurality of outer magnetrons may be different from a spacing between each adjacent magnetrons of the plurality of inner magnetrons.

Abstract: A light field imaging system with transparent photodetectors is presented. The light field imaging system includes: a stack of two or more detector planes, an imaging optic, and an image processor. The detector planes include one or more transparent photodetectors, such that transparent photodetectors have transparency greater than fifty percent (at one or more wavelengths) while simultaneously exhibiting responsivity greater than one amp per watt. The imaging optic is configured to receive light rays from a scene and refract the light rays towards the stack of two or more detector planes, such that the refracted light rays pass through the transparent detector planes and the refracted light rays are focused within the stack of detector planes. The image processor reconstruct a light field for the scene (at one of more wavelengths) using the light intensity distribution measured by each of the photodetectors.

Abstract: The present invention provides a method of fabricating a fin field effect transistor (finFET), comprising: firstly, an interfacial layer is formed on a fin structure, next, a high-k dielectric layer is formed on the interfacial layer; afterwards, a stress film is formed on the high-k dielectric layer, an annealing process is then performed to the stress film, and an etching process is performed to remove the stress film.

Abstract: A Hall-Effect measure apparatus comprises a magnetic source, a wafer on a thermal chuck, a dc current source and a voltage meter. The magnetic source generates a magnetic field in a perpendicular position relative to the wafer. Furthermore, the magnetic field is targeted at a specific region of the wafer to be tested. By performing a Hall-Effect measurement and van der Pauw measurement, the carrier mobility of the specific region of the wafer can be calculated.

Abstract: A spacer structure contains a carbon-containing oxide film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxide film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxide film.

Abstract: A Hall-Effect measure apparatus comprises a magnetic source, a wafer on a thermal chuck, a dc current source and a voltage meter. The magnetic source generates a magnetic field in a perpendicular position relative to the wafer. Furthermore, the magnetic field is targeted at a specific region of the wafer to be tested. By performing a Hall-Effect measurement and van der Pauw measurement, the carrier mobility of the specific region of the wafer can be calculated.

Abstract: A spacer structure contains a carbon-containing oxynitride film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxynitride film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxynitride film.

Abstract: A spacer structure contains a carbon-containing oxide film positioned on a gate sidewall and a nitride film covering the carbon-containing oxide film. The carbon-containing oxide film has low etch rate so that the spacer structure can have a good profile during etching the carbon-containing oxide film.

Abstract: A method of fabricating a MOS transistor is described. A substrate is provided, and then a composite layer for forming a gate structure and a carbon-containing mask material layer are formed thereon in turn, wherein the carbon-containing mask material layer is formed with a carbon-containing precursor gas and a reaction gas. The carbon-containing mask material layer and the composite layer are patterned into a carbon-containing hard mask layer and a gate structure, respectively. A spacer is formed on the sidewalls of the gate structure and the carbon-containing hard mask layer. A passivation layer is formed over the substrate, and then a portion of the passivation layer is removed to expose a portion of the substrate. A doped epitaxial layer is formed on the exposed portion of the substrate.

Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

Abstract: Fabrication methods for a MOS device and a CMOS device are provided. A substrate is provided with a gate structure formed on the substrate, a lightly-doped drain (LDD) region formed near sides of the gate structure in the substrate and a spacer wall formed on sidewalls of the gate structure and covering a part of the LDD region. A protection layer is formed for covering the gate structure, the LDD region and the spacer wall. A part of the protection layer is removed. Another part of the protection layer on the gate structure and the spacer wall is reserved. A part of the surface of the substrate is exposed. The exposed surface of the substrate is removed for forming a trench. A pre-clean step, including an oxygen plasma process, is performed on the bottom of the trench. An epitaxy material layer is formed in the trench.

Abstract: A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.