Abstract: An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.

Abstract: A semiconductor device and method for reducing dopant loss includes forming a gate electrode of an MOS transistor adjacent a semiconductor substrate. A relatively thin oxide screen layer is formed and disposed outwardly from the gate electrode. Nitrogen is then incorporated into the oxide screen layer. An upper dielectric layer is formed such that it is disposed outwardly from the nitrided oxide screen layer.

Abstract: An integrated circuit device (60) comprising a first transistor (PMOS) of a first conductivity type and a second transistor (NMOS) of a second conductivity type that is complementary to the first conductivity type. The method comprises the steps of forming a first gate stack (100), the first transistor comprising the first gate stack and forming a second gate stack (80), the second transistor comprising the second gate stack. The method further comprises implanting a first drain extension region (107) at a first distance relative to the first gate stack, the first transistor comprising the first drain extension region, and the method comprises implanting a second drain extension region (87) at a second distance relative to the second gate stack, the second transistor comprising the second drain extension region. The first distance is greater than the second distance.

Abstract: An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.

Abstract: An NMOS ESD clamping device and methods for making the same are disclosed in which the device includes N type drain and source regions formed in a semiconductor substrate and a gate overlying a P-type channel region in the substrate between the source and drain regions. A first silicide region is formed in the drain and/or the source region with a first thickness. A second thin silicide region is formed in the substrate between the gate and the drain having a second thickness less than the first thickness, wherein the thin silicide increases the ESD current clamping capability of the device to provide improved ESD circuit protection.

Abstract: Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.

Abstract: A method for forming a notched MOS gate structure is described. A multi-layer gate structure is formed (150) where the top layer (140) oxidizes at a faster rate compared to the bottom layer (130). This results in the formation of a notch (165) in the gate structure after thermal oxidation processes.

Abstract: A method for controlled oxide growth on transistor gates. A first film (40) is formed on a semiconductor substrate (10). The film is implanted with a first species and patterned to form a transistor gate (45) . The transistor gate (45) and the semiconductor substrate (10) is implanted with a second species and the transistor gate (45) oxidized to produce an oxide film (80) on the side surface of the transistor gate (45).

Abstract: A method for forming a ultra-shallow junction region (104). A silicon film (single crystalline, polycrystalline or amorphous) is deposited on the substrate (100) to form an elevated S/D (106). A metal film is deposited over the silicon film and reacted with the silicon film to form a silicide film (108). The silicon film is preferably completely consumed by the silicide film formation. An implant is performed to implant the desired dopant either into the metal film prior to silicide formation or into the silicide film after silicide formation. A high temperature anneal is used to drive the dopant out of the silicide film to form the junction regions (104) having a depth in the substrate (100) less than 200 Å. This high temperature anneal may be one of the anneals that are part of the silicide process or it may be an additional process step.