Patents by Inventor Che-Jen SU

Che-Jen SU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11836383
    Abstract: The present invention provides a storage device including a controller and methods for operating the storage device and the controller. A controller of a storage device may comprise: an interface controller; a memory controller; a processor configured to transmit downstream commands and upstream commands to the memory controller. The memory controller may be coupled between the interface controller and the processor and may comprise: a first command queue; a second command queue; and a tag generator. The memory controller may be configured to: store a first command received from the processor in the first command queue; store a second command received from the processor in the second command queue; and in response to a first access region of the first command overlapping a second access region of the second command in the second queue, assign an order tag to the second command based on a first serial number of the first command by the tag generator.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: December 5, 2023
    Assignee: SILICON MOTION INC.
    Inventors: Che Jen Su, Bao Ren Guo
  • Patent number: 10545876
    Abstract: A control unit for a data storage system is shown, which provides at least two buffers for updating mapping information through a host memory buffer HMB. A first buffer is provided for dynamic management of a physical-to-logical mapping table F2H that records a mapping relationship which maps a physical address within a target block to a logical address of a sector of user data stored at the physical address. The control unit performs reverse conversion on the mapping relationship to get reversed mapping information for the logical address and, accordingly, selects a target logical-to-physical mapping sub-table. A second buffer is provided to buffer the target logical-to-physical mapping sub-table when the target logical-to-physical mapping sub-table is read from the host memory buffer HMB. The control unit updates the target logical-to-physical mapping sub-table on the second buffer based on the reversed mapping information about the logical address.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 28, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Che-Jen Su
  • Publication number: 20190303299
    Abstract: A control unit for a data storage system is shown, which provides at least two buffers for updating mapping information through a host memory buffer HMB. A first buffer is provided for dynamic management of a physical-to-logical mapping table F2H that records a mapping relationship which maps a physical address within a target block to a logical address of a sector of user data stored at the physical address. The control unit performs reverse conversion on the mapping relationship to get reversed mapping information for the logical address and, accordingly, selects a target logical-to-physical mapping sub-table. A second buffer is provided to buffer the target logical-to-physical mapping sub-table when the target logical-to-physical mapping sub-table is read from the host memory buffer HMB. The control unit updates the target logical-to-physical mapping sub-table on the second buffer based on the reversed mapping information about the logical address.
    Type: Application
    Filed: November 5, 2018
    Publication date: October 3, 2019
    Inventor: Che-Jen SU