Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.

Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.

Abstract: A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.

Abstract: A bit line is pre-charged based on a clock signal internal to a bit line pre-charge circuit when a bit line pre-charge window is within a margin of a predetermined pre-charge window. A bit line is pre-charged based on a clock signal external to the bit line pre-charge circuit when the bit line pre-charge window is outside the margin of the predetermined pre-charge window.

Abstract: A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.

Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.

Abstract: A bit line is pre-charged based on a clock signal internal to a bit line pre-charge circuit when a bit line pre-charge window is within a margin of a predetermined pre-charge window. A bit line is pre-charged based on a clock signal external to the bit line pre-charge circuit when the bit line pre-charge window is outside the margin of the predetermined pre-charge window.

Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.

Abstract: A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.

Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.

Abstract: A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.

Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.

Abstract: A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.

Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.

Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.

Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.

Abstract: A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.

Abstract: A memory device includes a memory cell, a local bit line, a data line, first and second pass gate circuits, and a sense amplifier. The local bit line is coupled to the memory cell. The first pass gate circuit is coupled to the local bit line and the data line and is configured to couple the local bit line to the data line. The second pass gate circuit is coupled to the data line and the global bit line and is configured to couple the data line to the global bit line. The sense amplifier is coupled to the data line.

Abstract: A memory device includes a memory cell, a local bit line, a data line, first and second pass gate circuits, and a sense amplifier. The local bit line is coupled to the memory cell. The first pass gate circuit is coupled to the local bit line and the data line and is configured to couple the local bit line to the data line. The second pass gate circuit is coupled to the data line and the global bit line and is configured to couple the data line to the global bit line. The sense amplifier is coupled to the data line.

Abstract: A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.