Patents by Inventor Che Liang
Che Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240194848Abstract: The light emitting diode packaging structure includes a flexible substrate, micro light emitting elements disposed on the flexible substrate, a conductive pad, a redistribution layer, and an electrode pad. The micro light emitting elements have a first surface facing to the flexible substrate and a second surface opposite to the first surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting elements. The redistribution layer covers the micro light emitting elements and the conductive pad. The redistribution layer includes an insulating layer and a circuit layer embedded in the insulating layer. The circuit layer is electrically connected to the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer.Type: ApplicationFiled: February 27, 2024Publication date: June 13, 2024Inventors: Chih-Hao LIN, Jo-Hsiang CHEN, Shih-Lun LAI, Min-Che TSAI, Jian-Chin LIANG
-
Publication number: 20240177949Abstract: A force-sensitive key module and a force-sensitive switch structure are provided. The force-sensitive switch structure includes a first protective layer, a second protective layer, a first conductive layer, a second conductive layer and a force-sensitive layer. The first protective layer receives a pressing force. The second conductive layer is aligned with the first conductive layer. The force-sensitive layer is installed on the first conductive layer or the second conductive layer. When the first protective layer receives the pressing force, an electric connection between the first conductive layer and the second conductive layer is established, and the force-sensitive layer generates an analog sensing signal in response to the pressing force. When a magnitude of the pressing force is changed, the analog sensing signal is correspondingly changed according to an impedance change of the force-sensitive layer.Type: ApplicationFiled: February 22, 2023Publication date: May 30, 2024Inventors: Che-An Li, Yi-Liang Chen, Lei-Lung Tsai
-
Patent number: 11993512Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.Type: GrantFiled: March 14, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yang-Che Chen, Victor Chiang Liang, Chen-Hua Lin, Chwen-Ming Liu, Huang-Wen Tseng, Yi-Chuan Teng
-
Publication number: 20240139990Abstract: An internal rotor type nail drive device of electric nail gun, comprising a nailing rod and an internal rotor type rotary actuator that can output a specific rotation angle and can drive the nailing rod to move downward for nailing. Specifically, the rotary actuator comprises a stator and a rotor arranged inside the stator, even groups of electromagnetic mutual action components are configured in pairs between the stator and the rotor, to generate a tangential force to drive the rotor to rotate for a specific rotation angle, and to drive the nailing rod to move for a nailing stroke. The nailing stroke can be determined by a specific rotation angle. Thus, through the above configuration of the rotary actuator, the structure of the electric nail gun can be simplified, and the kinetic energy for nailing can be increased.Type: ApplicationFiled: August 22, 2023Publication date: May 2, 2024Inventors: I-TSUNG WU, CHIA-SHENG LIANG, YU-CHE LIN, WEN-CHIN CHEN
-
Publication number: 20240145581Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Chu LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
-
Patent number: 11973110Abstract: A semiconductor structure includes a substrate and a first capacitor. The substrate includes an active region. The first capacitor is over the substrate and free from overlapping the active region from a top view perspective.Type: GrantFiled: May 6, 2021Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Che-Yuan Chang, Hui-Zhong Zhuang, Chih-Liang Chen
-
Publication number: 20240136423Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.Type: ApplicationFiled: December 25, 2023Publication date: April 25, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou
-
Publication number: 20240128353Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ming Chang, Che-Hung Huang, Wen-Jung Liao, Chun-Liang Hou
-
Publication number: 20240127783Abstract: Provided are a noise cancellation method and apparatus, an electronic device, a noise cancellation earphone, and a storage medium. The method includes acquiring original sound source information; performing noise reduction (NR) processing on the original sound source information using active noise cancellation (ANC) to obtain first sound information and performing the NR processing on the original sound source information using environmental noise cancellation (ENC) to obtain second sound information; and mixing and adding the first sound information and the second sound information to obtain target sound information and playing the target sound information. In this method, the NR processing can be performed on the sound using the ANC and the ENC, thereby distinguishing environmental noise from human voice, improving the noise cancellation performance, and enabling a user to hear clearer sound.Type: ApplicationFiled: April 3, 2023Publication date: April 18, 2024Applicant: Lanto Electronic LimitedInventors: Che-Yung Huang, Chi-Liang Chen, Yong-Sheng Jheng, Che-Yi HSIAO
-
Patent number: 11951587Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.Type: GrantFiled: August 12, 2019Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Liang Chung, Che-Hao Tu, Kei-Wei Chen, Chih-Wen Liu
-
Patent number: 11949056Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, micro light emitting elements, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting elements are disposed on the first adhesive layer and have a first surface facing to the first adhesive layer and an opposing second surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting elements and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A thickness of the flexible substrate is less than 100 um.Type: GrantFiled: April 20, 2023Date of Patent: April 2, 2024Assignee: Lextar Electronics CorporationInventors: Chih-Hao Lin, Jo-Hsiang Chen, Shih-Lun Lai, Min-Che Tsai, Jian-Chin Liang
-
Publication number: 20240088054Abstract: A carrier structure is provided with a plurality of package substrates connected via connecting sections, and a functional element and a groove are formed on the connecting section, such that the groove is located between the package substrate and the functional element. Therefore, when a cladding layer covering a chip is formed on the package substrate, the groove can accommodate a glue material overflowing from the cladding layer to prevent the glue material from contaminating the functional element.Type: ApplicationFiled: December 8, 2022Publication date: March 14, 2024Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Shu-Ting LAI, Chiu-Lien LI, Che-Min SU, Chun-Huan HUNG, Mu-Hung HSIEH, Cheng-Han YAO, Fajanilan Darcyjo Directo, Cheng-Liang HSU
-
Publication number: 20240084455Abstract: Some implementations described herein include systems and techniques for fabricating a wafer-on-wafer product using a filled lateral gap between beveled regions of wafers included in a stacked-wafer assembly and along a perimeter region of the stacked-wafer assembly. The systems and techniques include a deposition tool having an electrode with a protrusion that enhances an electromagnetic field along the perimeter region of the stacked-wafer assembly during a deposition operation performed by the deposition tool. Relative to an electromagnetic field generated by a deposition tool not including the electrode with the protrusion, the enhanced electromagnetic field improves the deposition operation so that a supporting fill material may be sufficiently deposited.Type: ApplicationFiled: February 8, 2023Publication date: March 14, 2024Inventors: Che Wei YANG, Chih Cheng SHIH, Kuo Liang LU, Yu JIANG, Sheng-Chan LI, Kuo-Ming WU, Sheng-Chau CHEN, Chung-Yi YU, Cheng-Yuan TSAI
-
Patent number: 11923194Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.Type: GrantFiled: April 25, 2022Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang, Kuo-Hua Pan
-
Patent number: 11923455Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a fin structure, a gate electrode, a source-drain region, a plug and a hard mask structure. The gate electrode crosses over the fin structure. The source-drain region in the fin structure is aside the gate electrode. The plug is disposed over and electrically connected to the gate electrode. The hard mask structure surrounds the plug and is disposed over the gate electrode, wherein the hard mask structure includes a first hard mask layer and a second hard mask layer, the second hard mask layer covers a sidewall and a top surface of the first hard mask layer, and a material of the first hard mask layer is different from a material of the second hard mask layer.Type: GrantFiled: June 10, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Sheng Liang, Kuo-Hua Pan, Hsin-Che Chiang, Ming-Heng Tsai
-
Publication number: 20240066769Abstract: Provided is a decorated molding article includes a workpiece and a molded film attached to an outer surface of the workpiece or an inner surface of the workpiece. Compared with the printing layer in the conventional In Mold Label (IML) and InSert molding (INS) that is made by a plurality of anti-impact and bonding processes, a plurality of stacked decorative layers of the embodiment not only provide various color effects, but also directly combined with injection molding material to form part products and have both a protection effect and an adhesive effect. Further, the present disclosure can effectively simplify the manufacturing steps of the composite layer structure and reduce the manufacturing cost.Type: ApplicationFiled: June 28, 2023Publication date: February 29, 2024Applicant: Jin Ya Dian Technology Co.,Ltd.Inventors: Che-Ming Yu, Kuo-Liang Ying
-
Publication number: 20240066814Abstract: A method of manufacturing a decorated molding article includes: forming an all-in-one coating on a substrate and performing a curing step, thereby forming a composite layer structure with a protective effect, a color effect, and a bonding effect. Compared with the printing layer in the conventional In Mold Label (IML) and InSert molding (INS) that is made by a plurality of anti-impact and bonding processes, the composite layer structure of the embodiment can form a molded film with better physical properties (e.g., higher hardness, better protection effect, etc.) after the blister molding process. Therefore, the molded film of the embodiment can be applied to a laser engraving process to form a variety of light-transmitting decorative molded products. Further, the present disclosure further forms a protective layer locally in the grooves formed after the laser engraving process, so as to protect the texture after the laser engraving process from damage.Type: ApplicationFiled: February 9, 2023Publication date: February 29, 2024Applicant: Jin Ya Dian Technology Co.,Ltd.Inventors: Che-Ming Yu, Kuo-Liang Ying
-
Publication number: 20240023807Abstract: An optical biometer including a light source, a first-stage coupler, a first and a second second-stage coupler, a first and a second optical path difference generator, a first and a second optical component set, a first and a second detection device is disclosed. The first-stage coupler receives an incident light from the light source and emits first and second first-stage lights. The first second-stage coupler receives the first first-stage light and emits first and second second-stage lights. The second second-stage coupler receives the second first-stage light and emits third and fourth second-stage lights. The first/second optical path difference generator generates the first/fourth second-stage light with the first/second optical path difference. The first/second optical component set emits the second/third second-stage light to a first/second position of an eye and receives a first/second reflected light. The first/second detector receives a first/second detection light.Type: ApplicationFiled: July 13, 2023Publication date: January 25, 2024Inventors: Che-Liang TSAI, William WANG, Chung-Ping CHUANG, Sung-Yang WEI, Hsuan-Hao CHAO, Chung-Cheng CHOU
-
Publication number: 20230404403Abstract: An optical detection system capable of providing auxiliary light source projection including an optical detection apparatus and an optical module is disclosed. The optical module and the optical detection apparatus are combined with each other in a specific combination type. The specific combination type can be a direct integration type, a bending type, a foldable type, a low height type or an attachable type. The optical module is used to provide additional auxiliary light source projection to improve a condition for testee to gaze and observe a pattern. The optical module includes a light source, a lens set and a reflecting mirror. The light source can be designed as different types of multiple light sources, such as an opposite-direction type multiple light sources or a ring type multiple light sources, to provide a uniform light source.Type: ApplicationFiled: May 9, 2023Publication date: December 21, 2023Applicant: Crystalvue Medical CorporationInventors: Yen-Jen CHANG, William WANG, Che-Liang TSAI
-
Patent number: 11774241Abstract: Embodiments disclosed herein relate generally to methods for measuring a characteristic of a substrate. In an embodiment, the method includes scanning over the substrate with a scanning probe microscope, the substrate having fins thereon, the scanning obtaining images showing respective fin top regions of the fins, the scanning probe microscope interacting with respective portions of sidewalls of the fins by a scanning probe oscillated during the scanning, selecting images obtained at a predetermined depth below the fin top regions to obtain a line edge profile of the fins, by a processor-based system, analyzing the line edge profile of the fins using power spectral density (PSD) method to obtain spatial frequency data of the line edge profile of the fins, and by the processor-based system, calculating line edge roughness of the fins based on the spatial frequency data.Type: GrantFiled: December 15, 2021Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Shan Hu, Dong Gui, Jang Jung Lee, Che-Liang Li, Duen-Huei Hou, Wen-Chung Liu