Patents by Inventor Che-Liang Chung

Che-Liang Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11951587
    Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Liang Chung, Che-Hao Tu, Kei-Wei Chen, Chih-Wen Liu
  • Publication number: 20210166972
    Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 3, 2021
    Inventors: Che-Liang CHUNG, Che-Hao Tu, KEI-WEI CHEN, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
  • Patent number: 10943822
    Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Liang Chung, Che-Hao Tu, Kei-Wei Chen, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
  • Publication number: 20200094369
    Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.
    Type: Application
    Filed: August 12, 2019
    Publication date: March 26, 2020
    Inventors: Che-Liang Chung, Che-Hao Tu, Kei-Wei Chen, Chih-Wen Liu
  • Publication number: 20190287852
    Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventors: Che-Liang Chung, Che-Hao Tu, KEI-WEI CHEN, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
  • Patent number: 10160088
    Abstract: A method for polishing a polishing pad includes detecting a presence of a defect formed on a groove of a polishing pad; removing the defect from the groove of the polishing pad; after removing the defect, measuring a remaining depth of the groove; and based on the measured remaining depth of the groove, applying a polishing condition on the groove.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Liang Chung, Chun-Kai Tai, Shich-Chang Suen, Wei-Chen Hsiao
  • Patent number: 10164053
    Abstract: In an embodiment, a method includes: forming a gate stack on a semiconductor fin, the gate stack having gate spacers along opposing sides of the gate stack; forming source/drain regions adjacent the gate stack; recessing the gate stack to form a first recess between the gate spacers; depositing a dielectric layer over the gate stack in the first recess; forming a first metal mask over the dielectric layer and the gate stack in the first recess; etching back the dielectric layer and the gate spacers to form a dielectric mask under the first metal mask; depositing a conductive material over the first metal mask and adjacent the gate stack; and planarizing the conductive material to form contacts electrically connected to the source/drain regions, top surfaces of the contacts and the dielectric mask being level.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Liang Chung, Chi-Te Huang, Shich-Chang Suen, Kei-Wei Chen
  • Publication number: 20180043495
    Abstract: A method for polishing a polishing pad includes detecting a presence of a defect formed on a groove of a polishing pad; removing the defect from the groove of the polishing pad; after removing the defect, measuring a remaining depth of the groove; and based on the measured remaining depth of the groove, applying a polishing condition on the groove.
    Type: Application
    Filed: October 30, 2017
    Publication date: February 15, 2018
    Inventors: Che-Liang Chung, Chun-Kai Tai, Shich-Chang Suen, Wei-Chen Hsiao
  • Patent number: 9802292
    Abstract: A method for polishing a polishing pad includes detecting, by a first sensor, a presence of a defect formed on a groove of a polishing pad; removing, by a polishing disc, the defect from the groove of the polishing pad; after removing the defect, measuring, by a second sensor, a remaining depth of the groove; and based on the measured remaining depth of the groove, applying, through the polishing disc, a polishing condition on the groove.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Liang Chung, Shich-Chang Suen, Chun-Kai Tai, Wei-Chen Hsiao
  • Publication number: 20170239777
    Abstract: A method for polishing a polishing pad includes detecting, by a first sensor, a presence of a defect formed on a groove of a polishing pad; removing, by a polishing disc, the defect from the groove of the polishing pad; after removing the defect, measuring, by a second sensor, a remaining depth of the groove; and based on the measured remaining depth of the groove, applying, through the polishing disc, a polishing condition on the groove.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventors: Che-Liang Chung, Shich-Chang Suen, Chun-Kai Tai, Wei-Chen Hsiao