Patents by Inventor Che-Lun Hung

Che-Lun Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160041201
    Abstract: A die structure is described, including a device area and a contact test area. The device area has therein a device structure including a first contact plug. The contact test area has therein a contact test structure that includes a second contact plug and is different from the device structure. The contact test structure is also described, including a well, a heavily doped region in the well, and a contact plug, wherein the heavily doped region and the well are both of N-type or are both of P-type, and the contact plug is disposed over the heavily doped region.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 11, 2016
    Inventors: Che-Lun Hung, Hsiao-Leng Li
  • Publication number: 20150293169
    Abstract: Present example embodiments relate generally to methods, logic, systems, and devices for inspecting a semiconductor device. Example methods comprise applying an initial energy from an energy source to a first location of a conductive layer of the semiconductor device. Example methods further comprise measuring a resultant energy passing through the conductive layer using a probe at a second location of the conductive layer and analyzing the measured resultant energy passing through the conductive layer. Example methods further comprise determining a presence of an inconsistency in the conductive layer based on the analyzing.
    Type: Application
    Filed: April 14, 2014
    Publication date: October 15, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yen Chuang, Che-Lun Hung
  • Publication number: 20140253137
    Abstract: Methods and systems for the detection of defects in semiconductors, semiconductor devices, or substrates are provided. Semiconductors, semiconductor devices or substrates having novel test patterns and or designs are also provided. The semiconductors, semiconductor devices or substrates have a plurality of line patterns, which, in response to a responsive stimulus such as electron beam irradiation, produces a response. The responsive stimulus may include an electron beam irradiation, and the image data can be collected and processed to produce an image or images that indicate the presence or absence of surface and/or internal defects.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yen Chuang, Che-Lun Hung, Hsiao-Leng Li
  • Patent number: 8745234
    Abstract: A method and a manager physical machine (PM) for virtual machine (VM) consolidation are provided. The method is performed by the manager PM. A network connects the manager PM and a plurality of server PMs. A plurality of VMs is running on the server PMs. The method includes the following steps. The manager PM classifies the server PMs into redundant PMs and surviving PMs. The manager PM determines migration paths of the VMs running on the redundant PMs to the surviving PMs. The manager PM determines a parallel migration sequence of the VMs running on the redundant PMs based on the migration paths. The manager PM migrates the VMs running on the redundant PMs to the surviving PMs in parallel according to the parallel migration sequence.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: June 3, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Hsiao-Fei Liu, Tzi-Cker Chiueh, Jui-Hao Chiang, Che-Lun Hung
  • Patent number: 8594963
    Abstract: A method of predicting product yield may include determining defect characteristics for a product based at least in part on inspection data associated with critical layers of the product, determining yield loss for each of the critical layers, and estimating product yield based on the determined yield loss of the critical layers. A corresponding apparatus is also provided.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: November 26, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsiang-Chou Liao, Che-Lun Hung, Tuung Luoh, Ling-Wuu Yang, Ta-Hone Yang, Kuang-Chao Chen
  • Patent number: 8329480
    Abstract: A method of detecting manufacturing defects at a memory array may include disposing an active area of a first width in communication with a first conductive member of the memory array to define a grounded conductive member, disposing an isolation structure of a second width in communication with a second conductive member of the memory array to define a floating conductive member, and providing an alternating arrangement of floating and grounded conductive members including arranging a plurality of the grounded and floating conductive members adjacent to each other to define a sequence of alternating floating and grounded conductive members. A corresponding test device is also provided.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: December 11, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Che-Lun Hung, Hsiang-Chou Liao, Tuung Luoh, Ling-Wu Yang
  • Publication number: 20120166644
    Abstract: A method and a manager physical machine (PM) for virtual machine (VM) consolidation are provided. The method is performed by the manager PM. A network connects the manager PM and a plurality of server PMs. A plurality of VMs is running on the server PMs. The method includes the following steps. The manager PM classifies the server PMs into redundant PMs and surviving PMs. The manager PM determines migration paths of the VMs running on the redundant PMs to the surviving PMs. The manager PM determines a parallel migration sequence of the VMs running on the redundant PMs based on the migration paths. The manager PM migrates the VMs running on the redundant PMs to the surviving PMs in parallel according to the parallel migration sequence.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsiao-Fei Liu, Tzi-Cker Chiueh, Jui-Hao Chiang, Che-Lun Hung
  • Publication number: 20120074401
    Abstract: A method of detecting manufacturing defects at a memory array may include disposing an active area of a first width in communication with a first conductive member of the memory array to define a grounded conductive member, disposing an isolation structure of a second width in communication with a second conductive member of the memory array to define a floating conductive member, and providing an alternating arrangement of floating and grounded conductive members including arranging a plurality of the grounded and floating conductive members adjacent to each other to define a sequence of alternating floating and grounded conductive members. A corresponding test device is also provided.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 29, 2012
    Inventors: Che-Lun Hung, Hsiang-Chou Liao, Tuung Luoh, Ling-Wu Yang
  • Publication number: 20120053855
    Abstract: A method of predicting product yield may include determining defect characteristics for a product based at least in part on inspection data associated with critical layers of the product, determining yield loss for each of the critical layers, and estimating product yield based on the determined yield loss of the critical layers. A corresponding apparatus is also provided.
    Type: Application
    Filed: September 1, 2010
    Publication date: March 1, 2012
    Inventors: Hsiang-Chou Liao, Che-Lun Hung, Tuung Luoh, Ling-Wuu Yang, Ta-Hone Yang, Kuang-Chao Chen