Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region. The flip-flop also includes slave switch circuitry operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch perimeter resides within the flip-flop region and is non-overlapping with the master switch perimeter.

Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region. The flip-flop also includes slave switch circuitry operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter. The slave switch perimeter resides within the flip-flop region and is non-overlapping with the master switch perimeter.

Abstract: In some embodiments, a flip-flop is laid-out on a flip-flop region of a semiconductor substrate. The flip-flop includes master switch circuitry made of a first plurality of devices which are circumscribed by a master switch perimeter residing within the flip-flop region. Scan mux input circuitry is operably coupled to an input of the master switch circuitry. The scan mux input circuitry is made up of a second plurality of devices that are circumscribed by a scan mux perimeter which resides within the flip-flop region and which is non-overlapping with the master switch perimeter. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter which resides within the flip-flop region and which is non-overlapping with both the master switch perimeter and the scan mux perimeter.

Abstract: An exemplary flat panel display (1) includes a main body (10) and a transparent holding structure (12) fixed to the main body. The holding structure is configured to hold one or more thin insertions by itself at a side thereof and or by cooperation with the main body wherein one or more thin insertions are held between the holding structure and the main body at a side of the holding structure.

Abstract: An exemplary flat panel display (1) includes a display body (2), a neck (4), and at least one foot (6). The display body includes a back cover (20). The back cover includes a protruding portion (201), and a recessed portion (203) adjacent to the protruding portion. The neck is connected with the display body by a pivot (41), and corresponds to the recessed portion. The at least one foot is connected with the neck by a pivot assembly (42). The at least one foot supports the neck and the display body, and corresponds to the protruding portion. When the flat panel display is folded up, the neck is at least partially accommodated in the recessed portion, and the at least one foot is positioned a peripheral edge of the protruding portion.

Abstract: An exemplary flat panel display (1) includes a main body (10), a neck (11), and a base (12). The main body includes a chassis (17). The neck is connected with the chassis by a first pivot structure such that the main body can be rotated back and forth about a substantially horizontal axis. The base is connected with the neck by a second pivot structure such that the neck can be rotated left and right about a substantially vertical axis.

Abstract: An exemplary flat panel display (1) includes a display body (10) and a stand (12) supporting the display body. The stand includes a base (13), and a slider (14) slidably engaged to the base. The slider is configured for moving the display body upwardly or downwardly relative to the base.

Abstract: An exemplary on-screen display (OSD) controlling system (20) for a display device is provided. The system includes OSD buttons (22) without any symbols and an OSD menu (25) configured for displaying and adjusting characteristics of the display device. The OSD menu includes a primary OSD menu (211) and OSD submenus (213). The primary OSD menu displays first function icons (2112, 2113, 2114, 2115) denoting the display characteristics. Each function icon corresponds to at least one OSD submenu. Each OSD submenu includes second function icons (2141, 2142, 2143, 2144, 2145) configured to denote functions or movements of the corresponding OSD buttons. Each function icon of each OSD submenu corresponds to one OSD button.

Abstract: An exemplary flat panel display (1) includes a main body (10) and a transparent holding structure (12) fixed to the main body. The holding structure is configured to hold one or more thin insertions by itself at a side thereof and or by cooperation with the main body wherein one or more thin insertions are held between the holding structure and the main body at a side of the holding structure.

Abstract: An exemplary flat panel display (1) includes a display body (2), a neck (4), and at least one foot (6). The display body includes a back cover (20). The back cover includes a protruding portion (201), and a recessed portion (203) adjacent to the protruding portion. The neck is connected with the display body by a pivot (41), and corresponds to the recessed portion. The at least one foot is connected with the neck by a pivot assembly (42). The at least one foot supports the neck and the display body, and corresponds to the protruding portion. When the flat panel display is folded up, the neck is at least partially accommodated in the recessed portion, and the at least one foot is positioned a peripheral edge of the protruding portion.

Abstract: An exemplary flat panel display includes a display panel, a supporting member, and a base portion. The supporting member includes a main body portion and a bending portion extending substantially toward a front side of the display panel. The base portion adjoins the main body portion and the display panel has a jointing portion pivotally connected to the bending portion. The jointing portion of the display panel is located within a top half region of the display panel, such that the display panel and the supporting member define an accommodating space therebetween.