Patents by Inventor Che-Wei Jiang

Che-Wei Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hierarchy-based analytical placement method for an integrated circuit
    Patent number: 7984410
    Abstract: A placer produces a global placement plan specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) by initially clusterizing cell instances to form a pyramidal hierarchy of blocks and generating an initial global placement plan specifying a position of each block at a highest level of the hierarchy. The placer then declusterizes the global placement plan by replacing the highest level blocks with their component blocks and then improves the routability of the global placement plan by iteratively moving specified block positions in directions and by distances dynamically determined by analyzing the global placement plan and an objective function having a total wirelength term and having a bin density term reflecting density of blocks in specified areas (bins) of the IC.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: July 19, 2011
    Assignee: Springsoft USA, Inc.
    Inventors: Tung-Chieh Chen, Che-Wei Jiang
  • ANALYTICAL GLOBAL PLACEMENT FOR AN INTEGRATED CIRCUIT
    Publication number: 20090031269
    Abstract: A placer produces a global placement plan specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) by initially clusterizing cell instances to form a pyramidal hierarchy of blocks and generating an initial global placement plan specifying a position of each block at a highest level of the hierarchy. The placer then declusterizes the global placement plan by replacing the highest level blocks with their component blocks and then improves the routability of the global placement plan by iteratively moving specified block positions in directions and by distances dynamically determined by analyzing the global placement plan and an objective function having a total wirelength term and having a bin density term reflecting density of blocks in specified areas (bins) of the IC.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 29, 2009
    Applicant: SPRINGSOFT, INC.
    Inventors: Tung-Chieh Chen, Che-Wei Jiang