Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer is disposed on the die-attach surface. The first solder mask layer surrounds the semiconductor die. An additional circuit structure is disposed on a portion of the first solder mask, surrounding the semiconductor die. The additional circuit structure includes a pad portion having a first width and a via portion has a second width that is less than the first width. The via portion passes through the first solder mask layer to be coupled the redistribution layer (RDL) structure.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor die including a first active surface and a first non-active surface. The semiconductor package structure also includes a second semiconductor die including a second active surface and a second non-active surface. The second semiconductor die is stacked on the first semiconductor die. The first non-active surface faces the second non-active surface. The semiconductor package structure further includes a first redistribution layer (RDL) structure. The first active surface faces the first RDL structure. In addition, the semiconductor package structure includes a second RDL structure. The second active surface faces the second RDL structure.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package including a first redistribution layer (RDL) structure having a first surface and a second surface opposite to the first substrate. The first RDL structure includes a plurality of first conductive traces close to the first surface of the first RDL structure. An antenna pattern is disposed close to the second surface of the first RDL structure. A first semiconductor die is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. A plurality of conductive structures is disposed on the first surface of the first RDL structure and electrically coupled to the first RDL structure. The plurality of conductive structures is spaced apart from the antenna pattern through the plurality of first conductive traces of the first RDL structure.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.

Abstract: A semiconductor memory package is provided. The package includes a semiconductor die having a first die portion and a second die portion. A post-passivation layer is on the semiconductor die. A first post-passivation interconnect (PPI) structure includes pluralities of first and second pads arranged in first and second tiers, respectively. The first and second pads are disposed on a first die portion of the semiconductor die. A second PPI structure includes pluralities of third and fourth pads arranged in third and fourth tiers, respectively. The third and fourth pads are disposed on a second die portion of the semiconductor die. One of the first pads and one of the fourth pads are coupled to each other by a first bonding wire. One of the second pads and one of the third pads are coupled to each other.

Abstract: A system-in-package (SiP) includes a RDL structure having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side of the RDL structure, wherein the first semiconductor die has an active surface that is in direct contact with the RDL structure; a plurality of conductive fingers on the first side of the RDL structure around the first semiconductor die; a second semiconductor die stacked directly on the first semiconductor die, wherein the second semiconductor die is electrically connected to the plurality of conductive fingers through a plurality of bond wires; and a mold cap encapsulating the first semiconductor die, the conductive fingers, the second semiconductor die, and the first side of the RDL structure.

Abstract: An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view.

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a redistribution layer (RDL) structure die-attach surface and a bump-attach surface opposite the die-attach surface. A semiconductor die is mounted on the die-attach surface of the redistribution layer (RDL) structure. A first solder mask layer is disposed on the die-attach surface. The first solder mask layer surrounds the semiconductor die. An additional circuit structure is disposed on a portion of the first solder mask, surrounding the semiconductor die. The additional circuit structure includes a pad portion having a first width and a via portion has a second width that is less than the first width. The via portion passes through the first solder mask layer to be coupled the redistribution layer (RDL) structure.

Abstract: A flip chip package includes: a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein part of the copper column overhangs the via opening.

Abstract: A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.

Abstract: A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.

Abstract: A flip chip package includes: a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein part of the copper column overhangs the via opening.

Abstract: A flip chip package includes a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein the copper column is disposed on one side of the capture pad about the via opening only.

Abstract: A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.

Abstract: An exemplary flip-chip package is provided, including: a package structure having a first bonding pad and a second bonding pad formed thereon, wherein the first bond pad has a feature size different from a feature size of the second bond pad; a semiconductor chip facing the package structure, having a first under bump metal (UBM) layer and a second under bump metal (UBM) layer formed thereon, wherein the first UBM layer has a feature size different from a feature size of the second UBM layer; a first conductive element disposed between the first bond pad and the first UBM layer; and a second conductive element disposed between the second bond pad and the second UBM layer.

Abstract: A flip chip package includes a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein the copper column is disposed on one side of the capture pad about the via opening only.

Abstract: A structure of a package on package and a method for fabricating the same are provided. The structure of the package on package includes a first package, a second package and a plurality of pins. The first package includes a first substrate and a first chip disposed thereon. The second package includes a second substrate and a second chip disposed thereon. The second package is disposed under the first package. The second package includes a plurality of holes. The pins are disposed on the first package and inserted to the holes so as to electrically connect the first package and the second package.

Abstract: A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one opening is formed in a frame of the first packaging substrate correspondingly. Then, a second substrate unit is provided. The shape of the second substrate unit is different from the shape of the opening. Afterwards, the second substrate unit is disposed in the opening.