Abstract: A probe card and a manufacturing method of a probe card are provided. The probe card includes a probe head, first and second substrates, an insulating component, and an adhesive member. The second substrate is disposed between the probe head and the first substrate, and is disposed on the first substrate. The second substrate faces the first substrate and includes second contacts. The second contacts are electrically connected to first contacts of the first substrate. The insulating component is disposed between the first substrate and the second substrate, and disposed at an outer side of the second contacts. The adhesive member is disposed on the first substrate, arranged on at least a part of the side surface of the second substrate, and disposed at an outer side of the insulating component.

Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.

Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.

Abstract: A display panel and a pixel circuit thereof are provided. The pixel circuit includes a driving current generator, a pulse width signal generator, a voltage provider, and a current enabler. The driving current generator provides a driving current. The pulse width signal generator includes an output switch. The output switch is controlled by a control signal, and provides a pulse width signal according to the control signal. The voltage provider adjusts the control signal according to a data write-in signal and a pulse width modulation enable signal. The current enabler provides the driving current to a lighting component according to the pulse width signal and an amplitude modulation enable signal.

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.

Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.

Abstract: A deep trench structure may be formed between electrodes of a capacitive device. The deep trench structure may be formed to a depth, a width, and/or an aspect ratio that increases the volume of the deep trench structure relative to a trench structure formed using a metal etch-stop layer. Thus, the deep trench structure is capable of being filled with a greater amount of dielectric material, which increases the capacitance value of the capacitive device. Moreover, the parasitic capacitance of the capacitive device may be decreased by omitting the metal etch-stop layer. Accordingly, the deep trench structure (and the omission of the metal etch-stop layer) may increase the sensitivity of the capacitive device, may increase the humidity-sensing performance of the capacitive device, and/or may increase the performance of devices and/or integrated circuits in which the capacitive device is included.

Abstract: One or more semiconductor processing tools may form a deep trench within a silicon wafer. The one or more semiconductor processing tools may deposit a first insulating material within the deep trench. The one or more semiconductor processing tools may form, after forming the deep trench with the silicon wafer, a shallow trench above the deep trench. The one or more semiconductor processing tools may deposit a second insulating material within the shallow trench.

Abstract: An eye width monitor (EWM) for a clock and data recovery (CDR) circuit includes a delay circuit, a first multiplexer (MUX) and a calibration circuit. The delay circuit includes an input terminal and an output terminal. The first MUX, coupled to the delay circuit, includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the first MUX is coupled to a clock input terminal of the EWM. The second input terminal of the first MUX is coupled to the output terminal of the delay circuit. The output terminal of the first MUX is coupled to the input terminal of the delay circuit. The calibration circuit, coupled to the delay circuit, is configured to receive an oscillation clock from the delay circuit and receive a reference clock, and calibrate the oscillation clock with the reference clock.

Abstract: A method of filtering overlay data by field is provided in the present invention. The method includes the following steps. A minimum number of measure points per field on a semiconductor substrate is decided. Field data filtering rules are set. Overlay raw data is inputted. A raw data filtration is performed to the overlay raw data by field according to the field data filtering rules. Modified exposure parameters are generated for each field according to overlay data of remaining measure points per field after the raw data filtration when the number of the remaining measure points per field is larger than or equal to the minimum number of the measure points per field. Accordingly, the modified exposure parameters will be more effective in reducing the overlay error because more outliers may be filtered out before generating the modified exposure parameters.

Abstract: A super junction includes a substrate and an epitaxial layer over the substrate, the epitaxial layer having a first dopant type. The super junction further includes an angled trench in the epitaxial layer, the angled trench having sidewalls disposed at an angle ranging from about 85-degrees to about 89-degrees with respect to a top surface of the epitaxial layer. The super junction further includes a doped body in the epitaxial layer surrounding the angled trench, the doped body having a second dopant type, the second dopant type opposite that of the first dopant type.

Abstract: A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.

Abstract: An overlay mask includes a plurality of first patterns, a plurality of second patterns and a plurality of third patterns. The first patterns are arranged within a first pitch. The second patterns are arranged within a second pitch. A first portion of the third patterns are arranged alternately with the first patterns, within the first pitch, and a second portion of the third patterns are arranged alternately with the second patterns, within the second pitch, and the first pitch is not equal to the second pitch.

Abstract: A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.

Abstract: A method of filtering overlay data by field is provided in the present invention. The method includes the following steps. A minimum number of measure points per field on a semiconductor substrate is decided. Field data filtering rules are set. Overlay raw data is inputted. A raw data filtration is performed to the overlay raw data by field according to the field data filtering rules. Modified exposure parameters are generated for each field according to overlay data of remaining measure points per field after the raw data filtration when the number of the remaining measure points per field is larger than or equal to the minimum number of the measure points per field. Accordingly, the modified exposure parameters will be more effective in reducing the overlay error because more outliers may be filtered out before generating the modified exposure parameters.

Abstract: The present disclosure relates to an integrated circuit with a termination region, and an associated method of formation. In some embodiments, the integrated circuit comprises a cell region and a termination region. The termination region is disposed at an outer periphery of the cell region. The cell region comprises an array of device cells. The termination region comprises a plurality of termination rings encompassing the cell region. The plurality of termination rings have different depths.

Abstract: A method of fabricating a semiconductor structure for improving critical dimension control is provided in the present invention. The method includes the following steps. An inter metal dielectric (IMD) layer is formed on a semiconductor substrate, a patterned hard mask layer is formed on the IMD layer, and a first aperture is formed in the IMD layer. A first barrier layer is formed on the patterned hard mask layer and a surface of the first aperture, a first patterned resist is formed on the first barrier layer, and an etching process is performed to form a second aperture in the IMD layer by using the first patterned resist as a mask. The first patterned resist is kept from being poisoned because of the first barrier layer, and the critical dimension control of the semiconductor structure may be improved accordingly.