Patents by Inventor Che-Yi Su

Che-Yi Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11990111
    Abstract: A noise measuring device is provided. The noise measuring device includes a soundproof box, a sound receiving device, a holding device, and a driving device. The sound receiving device is disposed in the soundproof box. The holding device is disposed in the soundproof box and configured to hold a testing object. The driving device is connected with the soundproof box and configure to drive the soundproof box to rotate.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 21, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Sheng-Pin Su, Yuan-I Tseng, Che-Hung Lai, Chien-Yi Wang, Chuan-Te Chang
  • Patent number: 11990578
    Abstract: A LED display structure and its display module thereof are provided. The LED display module includes a LED array, a substrate disposed below the LED array, and at least one trace configuration layer, which is disposed below the LED array and adjacent to the substrate. The at least one trace configuration layer includes a plurality of wires, and a distribution density of the wires varies according to a distance between the wires and the LED array. When the distance increases, the distribution density of the wires is denser. Otherwise, the distribution density is sparse when the wires are closer to the LED array. In view of the simulation experimental analyses of the present invention, it is believed that at least 30% of the stray light ratio can be reduced so as to enhance the LED display structure with better transparency and image quality.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: May 21, 2024
    Assignees: INTERFACE TECHNOLOGY (CHENGDU) CO., LTD., INTERFACE OPTOELECTRONICS (SHENZHEN) CO., LTD., GENERAL INTERFACE SOLUTION LIMITED
    Inventors: Che Wen Chiang, Tsung Yi Su, Po Lun Chen
  • Publication number: 20230343493
    Abstract: In some embodiments, a multi-layer electrical device can include multiple electrodes connected to respective terminals, with at least two selected terminals being configured to allow movement relative to each other to accommodate a change in separation distance of the respective electrodes resulting from a change in temperature, and to allow a solder to provide a connection therebetween when the multi-layer electrical device is soldered on a mounting surface. In some embodiments, the multi-layer electrical device can further include a layer having a temperature-dependent electrical property implemented between each neighboring pair of electrodes.
    Type: Application
    Filed: July 4, 2023
    Publication date: October 26, 2023
    Inventors: Che-Yi SU, Jeff CHIEN, Stelar CHU, Simon CHUNG
  • Publication number: 20230178273
    Abstract: Devices and methods related to metal oxide varistor (MOV) having modified edge. In some embodiments, a MOV can include a metal oxide layer having first side and second sides, first and second electrodes implemented on the first and second sides of the metal oxide layer, respectively, with each electrode including a laterally inner portion and an edge portion. The edge portion of at least the first electrode can have a flared profile. In some embodiments, two of such MOVs can be joined to provide a sealed chamber defined by shapes of the first sides of the respective metal oxide layers and enclosing a gas therein, such that the sealed chamber with the gas and the first electrodes of the two MOVs form a gas discharge tube (GDT).
    Type: Application
    Filed: August 22, 2022
    Publication date: June 8, 2023
    Inventors: Kelly C. CASEY, Oscar ULLOA ESQUIVEL, Gordon L. BOURNS, Fernando ESTRADA HERNANDEZ, Che-Yi SU
  • Patent number: 7978171
    Abstract: A control circuit of a driving circuit for controlling a light emitting diode (LED) light source having a plurality of areas is provided. The control circuit includes the error amplifiers receiving a feed back current signal and a external reference voltage, and generating an error signal; a buffer register receiving a serial digital signal and generating the parallel digital signals; a work register receiving the parallel digital signals and a trigger signal, and outputting the parallel digital signals when the trigger signal is at a relatively high level; and a switch module having the power switches, each of which receives the error signal and the parallel digital signal for generating a driving signal to control a driving current of a specific area of the light source, in order to control the brightness in each area of the LED light source.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: July 12, 2011
    Assignee: Analog Integrations Corporation
    Inventors: Tsai-Fu Wu, Chang-Yu Wu, Chin-Feng Kang, Che-Yi Su
  • Publication number: 20080284714
    Abstract: A control circuit of a driving circuit for controlling a light emitting diode (LED) light source having a plurality of areas is provided. The control circuit includes the error amplifiers receiving a feed back current signal and a external reference voltage, and generating an error signal; a buffer register receiving a serial digital signal and generating the parallel digital signals; a work register receiving the parallel digital signals and a trigger signal, and outputting the parallel digital signals when the trigger signal is at a relatively high level; and a switch module having the power switches, each of which receives the error signal and the parallel digital signal for generating a driving signal to control a driving current of a specific area of the light source, in order to control the brightness in each area of the LED light source.
    Type: Application
    Filed: September 6, 2007
    Publication date: November 20, 2008
    Inventors: Tsai-Fu Wu, Chang-Yu Wu, Chin-Feng Kang, Che-Yi Su
  • Patent number: 7381283
    Abstract: The present invention mainly relates to a method for reducing shrinkage during sintering low-temperature-cofired ceramics, the ceramics comprising a dielectric portion and a heterogeneous material portion, the method comprising the steps of: (a) providing a monolithic structure, the monolithic structure comprising a dielectric body and a constraining layer; the dielectric body comprising at least one dielectric layer that comprises at least one active area; wherein said active area is disposed with at least one heterogeneous material pattern; the constraining layer positioned on the top of the dielectric body comprising at least one window wherein the edge of the active area of the dielectric layer each falls within the edge of the window in the vertical direction; (b) firing the monolithic structure; and (c) singulating the monolithic structure along a cutting line to provide the low-temperature-cofired ceramics, wherein the cutting line is disposed in the area formed between the edge of the window and the e
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: June 3, 2008
    Assignee: Yageo Corporation
    Inventors: Wen-Hsi Lee, Che-Yi Su, Chun-Te Lee
  • Patent number: 7138352
    Abstract: The present invention relates to a novel ZnTiO3-based dielectric material, having the composition represented by the formula (Zn1-aMga)(Ti1-b-cMnbDc)dO3, wherein D is an element having a valence of 5 or above, 0?a?0.5, c?b?0.1, 0<c?0.1, 1?d?1.5, which has properties of ultra low sintering temperature, high reliability, and high dielectric strength, and is capable of being applied to produce low capacitance multilayer ceramic capacitor with high quality factor, low ESR, and high insulation resistance. The present invention also relates to a method of preparing such a novel ZnTiO3-based dielectric material.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: November 21, 2006
    Assignee: Yageo Corporation
    Inventors: Wen-Hsi Lee, Che-Yi Su, Yi-Feng Yang
  • Publication number: 20060079391
    Abstract: The present invention relates to a novel ZnTiO3-based dielectric material, having the composition represented by the formula (Zn1-aMga)(Ti1-b-cMnbDc)dO3, wherein D is an element having a valence of 5 or above, 0?a?0.5, c?b?0.1, 0<c?0.1, 1?d?1.5, which has properties of ultra low sintering temperature, high reliability, and high dielectric strength, and is capable of being applied to produce low capacitance multilayer ceramic capacitor with high quality factor, low ESR, and high insulation resistance. The present invention also relates to a method of preparing such a novel ZnTiO3-based dielectric material.
    Type: Application
    Filed: January 21, 2005
    Publication date: April 13, 2006
    Applicant: Yageo Corporation
    Inventors: Wen-Hsi Lee, Che-Yi Su, Yi-Feng Yang
  • Patent number: 6893710
    Abstract: The present invention provides a multilayer ceramic composition comprising at least one layer of dielectric material M1 and at least one layer of dielectric material M2, wherein passive components are buried in both layers of dielectric material M1 and M2 that prevent each other from shrinkage in the X and Y dimensions during firing. Each layer of the multilayer ceramic composition according to the invention can be used as a substrate for burying the passive component and has the ability to prevent other layer with different dielectric constant from shrinkage. Hence, the multilayer ceramic composition has the advantages of smaller size and a better circuit precision.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: May 17, 2005
    Assignee: Yageo Corporation
    Inventors: Wen-Hsi Lee, Che-Yi Su, Yi-Jung Ling
  • Publication number: 20040209055
    Abstract: The present invention provides a multilayer ceramic composition comprising at least one layer of dielectric material M1 and at least one layer of dielectric material M2, wherein passive components are buried in both layers of dielectric material M1 and M2 that prevent each other from shrinkage in the X and Y dimensions during firing. Each layer of the multilayer ceramic composition according to the invention can be used as a substrate for burying the passive component and has the ability to prevent other layer with different dielectric constant from shrinkage. Hence, the multilayer ceramic composition has the advantages of smaller size and a better circuit precision.
    Type: Application
    Filed: April 18, 2003
    Publication date: October 21, 2004
    Applicant: Yageo Corpoartion
    Inventors: Wen-Hsi Lee, Che-Yi Su, Yi-Jung Ling
  • Publication number: 20040196638
    Abstract: The present invention mainly relates to a method for reducing shrinkage during sintering low-temperature-cofired ceramics, the ceramics comprising a dielectric portion and a heterogeneous material portion, the method comprising the steps of: (a) providing a monolithic structure, the monolithic structure comprising a dielectric body and a constraining layer; the dielectric body comprising at least one dielectric layer that comprises at least one active area; wherein said active area is disposed with at least one heterogeneous material pattern; the constraining layer positioned on the top of the dielectric body comprising at least one window wherein the edge of the active area of the dielectric layer each falls within the edge of the window in the vertical direction; (b) firing the monolithic structure; and (c) singulating the monolithic structure along a cutting line to provide the low-temperature-cofired ceramics, wherein the cutting line is disposed in the area formed between the edge of the window and the e
    Type: Application
    Filed: April 21, 2004
    Publication date: October 7, 2004
    Applicant: Yageo Corporation
    Inventors: Wen-Hsi Lee, Che-Yi Su, Chun-Te Lee
  • Publication number: 20030168150
    Abstract: The present invention mainly relates to a method for reducing X-Y shrinkage during sintering low temperature ceramic comprising piling a constrain layer on a dielectric layer on a green ceramic body, which is printed with heterogeneous materials for conductors, resistors, capacitors and the like and/or disposed conductors, resistors, capacitors and the like to reduce shrinkage of the dielectric layer and the green ceramic body. The invention is characterized in that the constrain layer comprises windows in positions complying with the heterogeneous materials and/or conductors, resistors, capacitors and the like printed and/or disposed on the dielectric layer and the green ceramic body to make the heterogeneous materials and/or conductors, resistors, capacitors and the like not being covered when piling the constrain layer and the dielectric layers of the green ceramic body.
    Type: Application
    Filed: August 20, 2002
    Publication date: September 11, 2003
    Applicant: Phycomp Taiwan Ltd
    Inventors: Wen-Hsi Lee, Che-Yi Su, Chun-Te Lee, Jui-Chu Jao