Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: A sequence detection device includes a decision-feedback equalizer (DFE), a combining circuit, a decision circuit, and a sequence detection circuit. The DFE processes a symbol decision signal to generate a first equalized signal. The combining circuit combines a data signal and the first equalized signal to generate a sample signal. The decision circuit performs hard decision upon the sample signal to generate the symbol decision signal. The sequence detection circuit performs sequence detection upon the data signal to generate and output a symbol sequence. Regarding the sequence detection, the sequence detection circuit selects branches for branch metric calculation according to at least the symbol decision signal.

Abstract: An error detection and correction device includes a decision-feedback equalizer (DFE), a decision circuit, an error detection circuit, and an error correction circuit. The DFE equalizes a data signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a symbol decision signal. The error detection circuit performs forward error detection at symbol positions of consecutive symbols included in the symbol decision signal to detect a head position of suspicious error that affects at least one symbol in the symbol decision signal. The error correction circuit performs error correction upon the symbol decision signal in response to the head position of the suspicious error that is detected by the error detection circuit.

Abstract: A sequence detection device includes a decision-feedback equalizer (DFE), a combining circuit, a decision circuit, and a sequence detection circuit. The DFE processes a symbol decision signal to generate a first equalized signal. The combining circuit combines a data signal and the first equalized signal to generate a sample signal. The decision circuit performs hard decision upon the sample signal to generate the symbol decision signal. The sequence detection circuit performs sequence detection upon the data signal to generate and output a symbol sequence. Regarding the sequence detection, the sequence detection circuit selects branches for branch metric calculation according to at least the symbol decision signal.