Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

Abstract: A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

Abstract: An electric connection is provided, and has a first copper (Cu) layer, a second Cu layer, and a composite metal layer disposed between the first Cu layer and the second Cu layer. The composite metal layer has 0.01 wt. %?gallium (Ga)?20 wt. %, 0.01 wt. %?copper (Cu)?50 wt. %, and 30 wt. %?nickel (Ni)?99.98 wt. %. Moreover, a method of manufacturing the electric connection is provided, and has the steps of: (1) providing a first Cu layer and a second Cu layer; (2) forming a first Ni layer on the first Cu layer; (3) forming a second Ni layer on the second Cu layer; (4) forming a Ga layer on the first Ni layer; and (5) keeping the second Ni layer in contact with the Ga layer and carrying out a thermo-compress bonding therebetween to form the electric connection.

Abstract: A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.

Abstract: Methods for forming semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a hard mask structure over a substrate and etching the substrate through an opening of the hard mask structure to form a trench. The method for manufacturing a semiconductor structure further includes removing a portion of the hard mask structure to enlarge the opening and forming an epitaxial-growth structure in the trench and the opening.

Abstract: Methods for forming semiconductor structures are provided. The method for manufacturing a semiconductor structure includes forming a hard mask structure over a substrate and etching the substrate through an opening of the hard mask structure to form a trench. The method for manufacturing a semiconductor structure further includes removing a portion of the hard mask structure to enlarge the opening and forming an epitaxial-growth structure in the trench and the opening.

Abstract: An electric connection is provided, and has a first copper (Cu) layer, a second Cu layer, and a composite metal layer disposed between the first Cu layer and the second Cu layer. The composite metal layer has 0.01 wt. %?gallium (Ga)?20 wt. %, 0.01 wt. %?copper (Cu)?50 wt. %, and 30 wt. %?nickel (Ni)?99.98 wt. %. Moreover, a method of manufacturing the electric connection is provided, and has the steps of: (1) providing a first Cu layer and a second Cu layer; (2) forming a first Ni layer on the first Cu layer; (3) forming a second Ni layer on the second Cu layer; (4) forming a Ga layer on the first Ni layer; and (5) keeping the second Ni layer in contact with the Ga layer and carrying out a thermo-compress bonding therebetween to form the electric connection.

Abstract: A semiconductor device comprises a substrate with a first side and a second side, wherein a plurality of active circuits are formed adjacent to the first side of the substrate and a plurality of through silicon vias arranged in a polygon shape and extending from the first side of to the second side, wherein the polygon shape has more than six sides, and wherein each through silicon via is placed at a corresponding apex of the polygon shape.