Patents by Inventor Che-Yuan Hsu

Che-Yuan Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250234581
    Abstract: A method of manufacturing a semiconductor device includes at least the following steps. An opening is formed in a substrate. A first protection layer is formed on an exposed surface of the opening. A first etching process is performed on the opening with the first protection layer thereon, to simultaneously remove the first protection layer on a sidewall of the opening and a portion of the substrate to deepen a depth of the opening.
    Type: Application
    Filed: April 6, 2025
    Publication date: July 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Patent number: 12294028
    Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.
    Type: Grant
    Filed: October 25, 2023
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Publication number: 20240387533
    Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Jiun-Ming Kuo, Pei-Ling Gao, Chen-Hsuan Liao, Hung-Ju Chou, Chih-Chung Chang, Che-Yuan Hsu
  • Publication number: 20240371649
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu
  • Patent number: 12136651
    Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Shan Lu, Hung-Ju Chou, Pei-Ling Gao, Chen-Hsuan Liao, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu
  • Patent number: 12131911
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20240236553
    Abstract: Actuator assemblies, and electronic devices and wearable devices including actuator assemblies, are disclosed. An actuator assembly includes: a first housing enclosing an audio actuator and a first open volume; and a second housing enclosing a haptic actuator and a second open volume. The first open volume is fluidly connected with the second open volume by an aperture between the first housing and the second housing. A first wall of the first housing abuts a second wall of the second housing. The aperture includes a first opening in the first wall of the first housing and a second opening in the second wall of the second housing. The first housing includes a linking component configured to mechanically connect to the second housing. The linking component includes a fluid conduit extending from the first open volume to an opening in the second wall of the second housing.
    Type: Application
    Filed: February 23, 2023
    Publication date: July 11, 2024
    Inventors: Jianxun Wang, Debanjan Mukherjee, Che-Yuan Hsu, Zhi Qiang Li, Michael Kai Morishita
  • Publication number: 20240087961
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Ju CHOU, Chih-Chung Chang, Jun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Kao, Chen-Hsuan Liao
  • Patent number: 11923250
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Publication number: 20240055527
    Abstract: A method of manufacturing a semiconductor device includes at least the following steps. A protrusion is formed in a substrate by an anisotropic etch process, wherein a sidewall of the protrusion is inclined. A recess is formed on the sidewall of the protrusion by an isotropic etch process, wherein during the isotropic etch process, a by-product covers a first portion of the sidewall of the protrusion while exposing a second portion of the sidewall of the protrusion, so that the recess is formed between the first portion and the second portion of the sidewall.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Publication number: 20240021612
    Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 18, 2024
    Inventors: Jiun-Ming Kuo, Pei-Ling Gao, Chen-Hsuan Liao, Hung-Ju Chou, Chih-Chung Chang, Che-Yuan Hsu
  • Publication number: 20230387213
    Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Yu-Shan Lu, Hung-Ju Chou, Pei-Ling Gao, Chen-Hsuan Liao, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu
  • Patent number: 11830948
    Abstract: A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Patent number: 11791336
    Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun-Ming Kuo, Pei-Ling Gao, Chen-Hsuan Liao, Hung-Ju Chou, Chih-Chung Chang, Che-Yuan Hsu
  • Patent number: 11705372
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Patent number: 11616133
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20230008005
    Abstract: The embodiments described herein are directed to a method for reducing fin oxidation during the formation of fin isolation regions. The method includes providing a semiconductor substrate with an n-doped region and a p-doped region formed on a top portion of the semiconductor substrate; epitaxially growing a first layer on the p-doped region; epitaxially growing a second layer different from the first layer on the n-doped region; epitaxially growing a third layer on top surfaces of the first and second layers, where the third layer is thinner than the first and second layers. The method further includes etching the first, second, and third layers to form fin structures on the semiconductor substrate and forming an isolation region between the fin structures.
    Type: Application
    Filed: July 28, 2022
    Publication date: January 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Ju Chou, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu, Pei-Ling Gao, Chen-Hsuan Liao
  • Publication number: 20220367200
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Application
    Filed: June 20, 2022
    Publication date: November 17, 2022
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20220262926
    Abstract: A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 18, 2022
    Inventors: Che-Lun Chang, Shiao-Shin Cheng, Ji-Yin Tsai, Yu-Lin Tsai, Hsin-Chieh Huang, Ming-Yuan Wu, Jiun-Ming Kuo, Ming-Jie Huang, Yu-Wen Wang, Che-Yuan Hsu
  • Patent number: 11387109
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu, deseased