Patents by Inventor CHEA OUK LIM

CHEA OUK LIM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818352
    Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and plurality of bit lines to corresponding rows and columns of the resistive memory cells. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance, which is greater than the first parasitic resistance.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-gyu Lee, Yong-jun Lee, Bilal Ahmad Janjua, Chea-ouk Lim, Makoto Hirano
  • Patent number: 10720209
    Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: July 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Kook Park, Young Hoon Oh, Chi Weon Yoon, Yong Jun Lee, Chea Ouk Lim
  • Patent number: 10706920
    Abstract: A memory device includes: a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells includes a switching element, and a data storage element connected to the switching element, wherein the data storage element includes a phase change material; and a memory controller configured to perform a control operation with respect to a first memory cell of the plurality of memory cells by inputting an operating current to the first memory cell, and inputting a compensation current flowing from the data storage element to the switching element in the first memory cell before or after inputting the operating current to the first memory cell.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chea Ouk Lim, Tae Hui Na, Jung Sunwoo, Yong Jun Lee
  • Publication number: 20200211671
    Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.
    Type: Application
    Filed: March 10, 2020
    Publication date: July 2, 2020
    Inventors: YONG-JUN LEE, TAE-HUI NA, CHEA-OUK LIM
  • Patent number: 10629286
    Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Jun Lee, Tae-Hui Na, Chea-Ouk Lim
  • Publication number: 20200098427
    Abstract: An integrated circuit memory device includes an array of resistive memory cells and a programming circuit, which is electrically coupled by a plurality of word lines and a plurality bit lines to corresponding rows and columns of resistive memory cells in the array. The programming circuit includes a control circuit and word line driver that are collectively configured to generate word line program voltages having magnitudes that vary as a function of the row and/or column addresses of the resistive memory cells in the array, during operations to program the array with write data. According to the function, the magnitude of a word line program voltage associated with a first resistive memory cell having a first parasitic resistance associated therewith is less than a magnitude of a word line program voltage associated with a second resistive memory cell having a second parasitic resistance associated therewith, which is greater than the first parasitic resistance.
    Type: Application
    Filed: May 16, 2019
    Publication date: March 26, 2020
    Inventors: Jun-gyu Lee, Yong-jun Lee, Bilal Ahmad Janjua, Chea-ouk Lim, Makoto Hirano
  • Patent number: 10580488
    Abstract: A memory device including: a memory cell array, including a memory cell having a switch element and a data storage element connected to the switch element, wherein the data storage element has a phase change material; and a memory controller for inputting a first read current to the memory cell to detect a first read voltage, inputting a second read current to the memory cell to detect a second read voltage, and inputting a compensation current to the memory cell, wherein the compensation current lowers a resistance value of the data storage element, the compensation current is input when a first state of the memory cell is different from a second state of the memory cell, the first state is determined using the first read voltage and the second state is determined using the second read voltage.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chea Ouk Lim, Tae Hui Na, Jung Sunwoo, Yong Jun Lee
  • Publication number: 20190172531
    Abstract: A memory device including: a memory cell array, including a memory cell having a switch element and a data storage element connected to the switch element, wherein the data storage element has a phase change material; and a memory controller for inputting a first read current to the memory cell to detect a first read voltage, inputting a second read current to the memory cell to detect a second read voltage, and inputting a compensation current to the memory cell, wherein the compensation current lowers a resistance value of the data storage element, the compensation current is input when a first state of the memory cell is different from a second state of the memory cell, the first state is determined using the first read voltage and the second state is determined using the second read voltage.
    Type: Application
    Filed: July 13, 2018
    Publication date: June 6, 2019
    Inventors: Chea Ouk Lim, Tae Hui Na, Jung Sunwoo, Yong Jun Lee
  • Publication number: 20190156909
    Abstract: A memory device includes a memory cell array, a write/read circuit, a control circuit and an anti-fuse array. The memory cell array includes a plurality of nonvolatile memory cells. The write/read circuit performs a write operation to write write data in a target page of the memory cell array, verifies the write operation by comparing read data read from the target page with the write data and outputs a pass/fail signal indicating one of a pass or a fail of the write operation based on a result of the comparing. The control circuit controls the write/read circuit and selectively outputs an access address of the target page as a fail address in response to the pass/fail signal. The anti-fuse array in which the fail address is programmed, outputs a repair address that replaces the fail address.
    Type: Application
    Filed: September 12, 2018
    Publication date: May 23, 2019
    Inventors: Yong-Jun Lee, Tae-Hui Na, Chea-Ouk Lim
  • Publication number: 20190130969
    Abstract: A memory device includes: a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells includes a switching element, and a data storage element connected to the switching element, wherein the data storage element includes a phase change material; and a memory controller configured to perform a control operation with respect to a first memory cell of the plurality of memory cells by inputting an operating current to the first memory cell, and inputting a compensation current flowing from the data storage element to the switching element in the first memory cell before or after inputting the operating current to the first memory cell.
    Type: Application
    Filed: August 10, 2018
    Publication date: May 2, 2019
    Inventors: CHEA OUK LIM, Tae Hul Na, Jung Sunwoo, Yong Jun Lee
  • Publication number: 20190108880
    Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 11, 2019
    Inventors: HYUN KOOK PARK, YOUNG HOON OH, CHI WEON YOON, YONG JUN LEE, CHEA OUK LIM
  • Patent number: 10181348
    Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: January 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Kook Park, Young Hoon Oh, Chi Weon Yoon, Yong Jun Lee, Chea Ouk Lim
  • Patent number: 10074426
    Abstract: A memory device having a resistance change material and an operating method of the memory device are provided. A memory device includes a memory cell array including first and second resistive memory cells, which store different data according to the change of their resistance; a buffer including first and second storage regions corresponding to the first and second resistive memory cells, respectively; and a control circuit receiving program data to be programmed to the memory cell array, comparing first data stored in the first storage region and second data stored in the first resistive memory cell, and as a result of the comparison determining one of the first and second storage regions as a storage region to which to write the program data.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: September 11, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chea Ouk Lim, Hyun Kook Park, Jung Sunwoo, Young Hoon Oh, Yong Jun Lee
  • Publication number: 20180204616
    Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.
    Type: Application
    Filed: August 15, 2017
    Publication date: July 19, 2018
    Inventors: HYUN KOOK PARK, YOUNG HOON OH, CHI WEON YOON, YONG JUN LEE, CHEA OUK LIM
  • Publication number: 20180197602
    Abstract: A memory device having a resistance change material and an operating method of the memory device are provided. A memory device includes a memory cell array including first and second resistive memory cells, which store different data according to the change of their resistance; a buffer including first and second storage regions corresponding to the first and second resistive memory cells, respectively; and a control circuit receiving program data to be programmed to the memory cell array, comparing first data stored in the first storage region and second data stored in the first resistive memory cell, and as a result of the comparison determining one of the first and second storage regions as a storage region to which to write the program data.
    Type: Application
    Filed: August 15, 2017
    Publication date: July 12, 2018
    Inventors: CHEA OUK LIM, HYUN KOOK PARK, JUNG SUNWOO, YOUNG HOON OH, YONG JUN LEE