Patents by Inventor Chee Cheong Wong

Chee Cheong Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9110021
    Abstract: A method and a system for the enhancement of the sensitivity in surface plasmon resonance (SPR) sensors based metallic grating by exploiting the conical configuration is presented. We consider the propagation of surface plasmon polaritons (SPPs) excited by light from the visible to infrared spectrum range, incident on a plasmonic grating at different directions by varying both the zenith and azimuthal angles. For specific azimuthal angles, SPPs propagate in the grating plane perpendicular to the incident light momentum. This is the condition that allows increasing the number of different excited SPPs modes largely. We exploit this effect to increase the sensor sensitivity with the change of refractive index of thin film on the plasmonic grating surface. Polarization effects also contribute to a further modes enhancement and increase the sensitivity. A scheme for a lab-on-chip implementation of a system that allows a parallel detection in microfluidic channels has been shown.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: August 18, 2015
    Assignee: Universita degli Studi di Padova
    Inventors: Filippo Romanato, Gianluca Ruffato, Chee Cheong Wong, Lee Kwang Hong, Husen Kartasamita Kang
  • Publication number: 20120002203
    Abstract: A method and a system for the enhancement of the sensitivity in surface plasmon resonance (SPR) sensors based metallic grating by exploiting the conical configuration is presented. We consider the propagation of surface plasmon polaritons (SPPs) excited by light from the visible to infrared spectrum range, incident on a plasmonic grating at different directions by varying both the zenith and azimuthal angles. For specific azimuthal angles, SPPs propagate in the grating plane perpendicular to the incident light momentum. This is the condition that allows increasing the number of different excited SPPs modes largely. We exploit this effect to increase the sensor sensitivity with the change of refractive index of thin film on the plasmonic grating surface. Polarization effects also contribute to a further modes enhancement and increase the sensitivity. A scheme for a lab-on-chip implementation of a system that allows a parallel detection in microfluidic channels has been shown.
    Type: Application
    Filed: March 8, 2010
    Publication date: January 5, 2012
    Applicants: NANYANG TECHNOLOGICAL UNIVERSITY, UNIVERSITÀ DEGLI STUDI DI PADOVA
    Inventors: Filippo Romanato, Gianluca Ruffato, Chee Cheong Wong, Lee Kwang Hong, Husen Kartasamita Kang
  • Publication number: 20110226841
    Abstract: A method for forming direct metal-metal bond between metallic surfaces is disclosed. The method comprises depositing a first nanostructured organic coating (118) on a first metallic surface (116) to form a first passivation layer thereon, the first nanostructured organic coating (118) comprising an organic phase with nanoparticles dispersed within the organic phase, contacting the first nanostructured organic coating (118) with a second metallic surface (126), and applying on the first and second metallic surfaces (116, 126) at least a bonding temperature of at least room temperature and/or a bonding pressure for a bonding period to bond the first and second metallic surfaces (116, 126) thereby forming the direct metal-metal bond therebetween. A second nanostructured organic coating (128) comprising an organic phase with nanoparticles dispersed within the organic phase may also be deposited on the second metallic surface (126).
    Type: Application
    Filed: November 27, 2008
    Publication date: September 22, 2011
    Inventors: Jun Wei, Xiao Fang Ang, Chee Cheong Wong, Zhong Chen
  • Patent number: 6121065
    Abstract: A method of facilitating wafer level burn-in testing. The method may utilize a rerouting process to connect input and output connections of each chip on the wafer to a bus network. The bus network may be used to conduct wafer level burn-in testing and does not change the AC/DC operating characteristics of the chips.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: September 19, 2000
    Assignee: Institute of Microelectronics
    Inventors: Chee Cheong Wong, Shun Shen Peter Wang