Abstract: At least one aspect is directed to a power supply. The power supply includes one or more unregulated voltage converters. Each unregulated voltage converter includes a switched block producing an output voltage across its output terminals. The power supply includes a voltage supply input coupled to at least one of the unregulated voltage converters, and an unregulated voltage bus coupled to at least one of the unregulated voltage converters. The power supply includes a voltage regulator coupled to the unregulated voltage bus and producing a regulated voltage across its output terminals. The output terminals of the voltage regulator are connected in parallel to the output terminals of at least one of the unregulated voltage converters. This can produce a regulated output voltage across a pair of power supply output terminals.

Abstract: A method for forming a via in an integrated circuit packaging substrate includes embedding an interfacial adhesion layer at a base of a via, and heating the materials at the base of the via. Embedding the interfacial adhesion layer further includes placing a conductive material over the interfacial adhesion layer. An interfacial layer material is deposited within at the base of opening and a conductive material is placed over the interfacial material. The interfacial layer material is a material that will diffuse into the conductive material at the temperature produced by heating the materials at the base of the via opening. Heating the materials at the base of the via opening includes directing energy from a laser at the base of the opening. An integrated circuit packaging substrate includes a first layer of conductive material, and a second layer of conductive material.

Abstract: The characteristics of a radio frequency package having short path length and the characteristics of a logic or memory package may be combined so that a high input/output connection is provided together with good radio frequency performance. In some embodiments, a non-radio frequency logic or memory die may be stacked on top of a larger radio frequency die. The radio frequency die may be connected to conventional quad flat no-lead lands. The non-radio frequency or logic or memory die may be connected to conventional leads. In some cases, some contacts on the radio frequency integrated circuit may be connected to leads as well, increasing the input/output capabilities of the radio frequency die.

Abstract: A ball grid array device includes an array of pads made of an electrically conductive material. The array of pads is positioned on the first major surface. At least one of the array of pads includes a diffusion retarding layer to retard the rate of diffusion of the electrically conductive material from the pad. The ball grid array device also includes a binding layer for binding the diffusion retarding layer to the conductive material of the at least one pad. The ball grid array device also includes a layer of material for receiving solder placed on the diffusion retarding layer.

Abstract: A ball grid array device includes a substrate, further including a first major surface and a second major surface. An array of pads is positioned on one of the first major surface or the second major surface. At least some of the pads include a barrier layer having pores or openings therein. When solder is placed on the pad, the barrier layer forms an intermetallic compound at a rate different from the rate of the intermetallic compound formed between the pad and the solder. The result is a solder ball on a pad that has a first intermetallic compound and a second intermetallic compound.