Abstract: An Accelerated Storage Controller (ASC) in an electronic device allows both conventional (slower) application processor to memory interfaces to be employed transparently to existing software, while also allowing software configuration to realize an accelerated storage architecture on demand. Some use cases for the electronic device do not require accelerated storage, and a bypass mode does not require any modification to existing software. Other use cases (such as fast download of multiple gigabytes of media) benefit from an accelerated storage architecture offloading transfer from the electronic device application processor, but could also work with the traditional processor to memory interface, at the cost of slower downloads. Embodiments of the present invention provide for both these possibilities in a software-configurable architecture. Furthermore, a number of other connectivity options are provided under software control to optimize performance and connectivity for different use case scenarios.

Abstract: An Accelerated Storage Controller (ASC) in an electronic device allows both conventional (slower) application processor to memory interfaces to be employed transparently to existing software, while also allowing software configuration to realize an accelerated storage architecture on demand. Some use cases for the electronic device do not require accelerated storage, and a bypass mode does not require any modification to existing software. Other use cases (such as fast download of multiple gigabytes of media) benefit from an accelerated storage architecture offloading transfer from the electronic device application processor, but could also work with the traditional processor to memory interface, at the cost of slower downloads. Embodiments of the present invention provide for both these possibilities in a software-configurable architecture. Furthermore, a number of other connectivity options are provided under software control to optimize performance and connectivity for different use case scenarios.

Abstract: An embedded host controller, for use in a USB system comprising a processor and an associated system memory, comprises a DMA controller, and the host controller is adapted such that, in order to retrieve data from the associated system memory, a starting address and block length are sent to the DMA controller, and the DMA controller is adapted such that, on receipt of a starting address and block length sent from the host controller, it retrieves the indicated data from the associated system memory. This has the advantage that the embedded host controller can be used with different host microprocessors, without assuming that PCI functionality is available.