Patents by Inventor Chee-Hau Ng

Chee-Hau Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240047266
    Abstract: A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Liang Liao, Chee Hau Ng, Ching-Yang Wen, Purakh Raj Verma
  • Publication number: 20240038832
    Abstract: A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.
    Type: Application
    Filed: August 21, 2022
    Publication date: February 1, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, Chee-Hau Ng, Chin-Wei Ho
  • Publication number: 20230268246
    Abstract: A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 24, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Liang Liao, Purakh Raj Verma, Ching-Yang Wen, Chee Hau Ng
  • Patent number: 11670567
    Abstract: A semiconductor structure includes a glass substrate and a device wafer. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: June 6, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Liang Liao, Purakh Raj Verma, Ching-Yang Wen, Chee Hau Ng
  • Patent number: 11398548
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 26, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
  • Publication number: 20220013430
    Abstract: A semiconductor structure includes a glass substrate and a device wafer. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 13, 2022
    Inventors: Chia-Liang Liao, Purakh Raj Verma, Ching-Yang Wen, Chee Hau Ng
  • Publication number: 20210104602
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.
    Type: Application
    Filed: December 16, 2020
    Publication date: April 8, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
  • Patent number: 10903314
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 26, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
  • Patent number: 10622253
    Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: April 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Da Huang, Wei-Hui Gao, Chien-Kee Pang, Wen-Bo Ding, Sheng Zhang, Wen-Shen Li, Chee-Hau Ng, Xiaoyuan Zhi
  • Publication number: 20190378757
    Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 12, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Li-Da Huang, Wei-Hui Gao, Chien-Kee Pang, Wen-Bo Ding, Sheng Zhang, Wen-Shen Li, Chee-Hau Ng, Xiaoyuan Zhi
  • Publication number: 20190355812
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.
    Type: Application
    Filed: June 25, 2018
    Publication date: November 21, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng