Abstract: A package and method is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, and an encapsulant at least partially encapsulating the electronic component and partially encapsulating the carrier. At least a portion of a bottom surface and at least a portion of a sidewall of the carrier are exposed beyond the encapsulant. Said at least portion of the bottom surface and said at least portion of the sidewall are covered at least partially by a plating structure.

Abstract: A molded power package includes a laser-activatable mold compound having laser-activated regions which are plated with an electrically conductive material to form metal pads and/or metal traces at a first side of the mold compound. A semiconductor power die with bond pads is embedded in the laser-activatable mold compound. A bond pad interconnect electrically connects the bond pads of the semiconductor power die to the metal pads and/or metal traces at the first side of the laser-activatable mold compound. The semiconductor power die is mounted on a carrier section of a leadframe. A carrier interconnect section of the leadframe integral with the carrier section electrically connects the carrier section to the metal pads and/or metal traces at the first side of the laser-activatable mold compound. An upper surface of the carrier interconnect section is at a height that is elevated relative to an upper surface of the carrier section.

Abstract: A power die package includes a power die having a plurality of bond pads at an upper surface of the power die. The package further includes a plurality of contact structures. A contact structure includes: a bond wire bonded to one of the plurality of bond pads and folded back to the bond pad to form a closed loop, or at least three bumps laterally spaced from one another and disposed on one or more bond pads; and a continuous longitudinally extended electrically conductive element connected to the at least three bumps in at least three contact positions. The conductive element bends away from the power die between pairs of consecutive contact positions. The package further includes a mold compound partially encapsulating the contact structure. The mold compound includes an outer surface facing away from the power die. The contact structure is partially exposed at the outer surface.

Abstract: A package includes: a vertically extending first electronic component with at least one exposed electrically conductive first terminal; a vertically extending second electronic component with at least one exposed electrically conductive second terminal; and a clip with an accommodation volume in which the first electronic component and the second electronic component are accommodated and are held together. The at least one first terminal and the at least one second terminal are electrically accessible at a bottom of the clip.

Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.

Abstract: The invention, in part, encompasses methods to assess viral infections in cells and subjects. The invention includes methods that can be used to determine the presence or absence of a viral infection in a cell or subject; severity of a viral infection in a cell or subject, and/or risk of a severe viral infection in a cell or subject. Certain methods of the invention also include selecting and/or administration a therapeutic regimen for a subject with a viral infection, based in part on the determination of the presence and/or severity of the viral infection in the subject.

Abstract: Examples disclose a semiconductor package including a semiconductor chip, an encapsulation, and a metal structure. The semiconductor chip is at least partially embedded in the encapsulation. The metal structure is formed on an outer surface of the encapsulation and includes a floating portion. The floating portion is floating on the encapsulation and the metal structure is electrically coupled with the semiconductor chip. Further examples disclose a method for manufacturing a semiconductor package, the method including providing a semiconductor chip at least partially embedded in an encapsulation; providing a metal structure on the encapsulation; forming a floating portion of the metal structure by forming a recess in the encapsulation.

Abstract: A power semiconductor package includes: a first power semiconductor die arranged on and electrically coupled to a first side of a first die pad; a first passive electronic component having a first end and an opposite second end, the first end being arranged on and coupled to the first side of the first die pad and the second end being coupled to an internal ledge of a first external contact; a second passive electronic component connected in series with the first passive electronic component; and an encapsulation encapsulating the first power semiconductor die and the first and second passive electronic components. The first external contact is exposed from a first lateral side of the encapsulation.

Abstract: A method of forming a semiconductor package includes providing a baseplate, mounting a semiconductor die on the baseplate with a main surface of the semiconductor die facing away from the baseplate, forming vertical interconnect elements on the main surface of the semiconductor die, forming an encapsulant on the baseplate that encapsulates the semiconductor die, exposing the vertical interconnect elements at an upper surface of the encapsulant, forming a first level metal pad on the upper surface of the encapsulant that contacts the exposed vertical interconnect elements, and forming structured metal regions on the upper surface of the encapsulant, wherein forming the structured metal regions includes structuring the first level metal pad.

Abstract: Integrated circuit devices, methods, and circuitry for selectively blocking a voltage signal on receiver circuitry to reduce or eliminate unequal aging on the receiver circuitry. A device may include a first input/output (IO) pin to receive a first voltage and a second IO pin to receive a second voltage. The device may include a differential signal receiver that includes a first terminal coupled to the first IO pin and a second terminal coupled to the second IO pin. Transmission gate circuitry may selectively block the first voltage or the second voltage from being applied to the differential signal receiver. The transmission gate circuitry may include transistors having a lower junction voltage limit than the first voltage or the second voltage, or both.

Abstract: A receiver circuit includes a first sense amplifier circuit that generates a first data signal based on a second data signal that has a first common-mode voltage during a first mode of operation. The receiver circuit includes a second sense amplifier circuit that generates a third data signal based on a fourth data signal that has a second common-mode voltage less than the first common-mode voltage during a second mode of operation. The receiver circuit includes a switch circuit that provides first data bits indicated by the first data signal to an output during the first mode of operation. The switch circuit provides second data bits indicated by the third data signal to the output during the second mode of operation.

Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.

Abstract: Disclosed is a capacitor having a high dielectric constant and low leakage current and a method for fabricating the same, wherein the capacitor may include a first conductive layer, a second conductive layer, a dielectric layer stack between the first conductive layer and the second conductive layer, a dielectric interface layer between the dielectric layer stack and the second conductive layer, and a high work function interface layer between the dielectric interface layer and the second conductive layer.

Abstract: A package is disclosed. In one example, the package includes an electronic component and an encapsulant encapsulating at least part of the electronic component. A first electrically conductive structure is arranged on one side of the electronic component, a second electrically conductive structure arranged on an opposing other side of the electronic component and being electrically coupled with the electronic component, and at least one sidewall recess at the encapsulant. The first electrically conductive structure and the second electrically conductive structure are configured to be at different electric potentials during operation of the package. The first electrically conductive structure and the second electrically conductive structure are exposed at opposing main surfaces of the encapsulant.

Abstract: Disclosed is a capacitor having a high dielectric constant and low leakage current and a method for fabricating the same, wherein the capacitor may include a first conductive layer, a second conductive layer, a dielectric layer stack between the first conductive layer and the second conductive layer, a dielectric interface layer between the dielectric layer stack and the second conductive layer, and a high work function interface layer between the dielectric interface layer and the second conductive layer.

Abstract: A method for fabricating an electronic device includes providing an encapsulant having an encapsulation material, providing a first laser beam and forming a trench into a main surface of the encapsulant by removing the encapsulation material by means of the first laser beam, forming a mask along a portion above the edge of the trench, and providing a second laser beam and sweeping the second laser beam over a surface area of the main surface of the encapsulant, wherein the surface area covers at least an area spatially confined by the trench.

Abstract: A method of forming a semiconductor package includes providing a metal baseplate having a base section and a plurality of metal posts, the base section being a planar pad of substantially uniform thickness, the plurality of metal posts each extending up from a planar upper surface of the base section, mounting a semiconductor die on the upper surface of the metal baseplate, forming an encapsulant body of electrically insulating mold compound on the upper surface of the base section, electrically connecting terminals of the semiconductor die to the metal posts, and removing the base section so as to form package contacts from the metal posts at a first surface of the encapsulant body.