Patents by Inventor Chee Kiang Goh

Chee Kiang Goh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11362966
    Abstract: Examples include a method of identifying single twisted pair cable Ethernet auto-negotiation requests or double twisted pair cables Ethernet auto-negotiation requests using detection of message time interval patterns. The method includes receiving, by a first Ethernet device, a plurality of messages transmitted by a second Ethernet device over a single twisted pair cable connecting the first Ethernet device and the second Ethernet device; storing one or more time intervals between starting times of successive pairs of the plurality of messages; determining if a pattern is found in the time intervals; when the pattern is found, setting a single twisted pair cable communications mode between the first Ethernet device and the second Ethernet device; and performing priority resolution between the first Ethernet device and the second Ethernet device.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: Chee-kiang Goh, Mario Traeber
  • Patent number: 11349523
    Abstract: A device comprises a clock source configured to provide a spread-spectrum modulated clock signal and a control signal associated with the spread-spectrum modulated clock signal. The device also comprises a circuitry configured to receive the spread-spectrum modulated clock signal, to receive the control signal, and to sample a data signal in accordance with the spread-spectrum modulated clock signal and the control signal.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Chee Kiang Goh, Mario Traeber
  • Publication number: 20210367710
    Abstract: A method and apparatus for sending side-channel bits on an Ethernet cable. An Ethernet device includes an encoder, a controller, and a signal processor. The encoder may encode payload bits to generate an encoded frame including the payload bits, zero bits, and parity bits. The zero bits are added to the payload bits before encoding. The controller may send side-channel data to the encoder so that the zero bits are replaced with the side-channel bits. The signal processor modulates the encoded frame with the side-channel bits and transmit on an Ethernet cable. The payload bits may be encoded by using low density parity check (LDPC) (1723,2048) code.
    Type: Application
    Filed: December 20, 2018
    Publication date: November 25, 2021
    Inventors: Eric MOUCHEL LA FOSS, Biju SUKUMARAN, Chee Kiang GOH
  • Patent number: 10747538
    Abstract: An Ethernet device comprises a plurality of Management Data Input/Output (MDIO) Manageable Device (MMD) registers storing Ethernet register field definitions that operate a management interface to one or more MMD devices. An MDIO controller, communicatively coupled to the plurality of MMD registers can control communication via the management interface to the one or more MMD devices based on a mapping of the set of Ethernet register field definitions to the plurality of MMD registers, and dynamically modify the mapping of the set of Ethernet register field definitions to the plurality of MMD registers.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Eric Mouchel La Fosse, Paul Louis Chazhoor, Chee Kiang Goh, Hak Keong Sim
  • Publication number: 20200201637
    Abstract: An Ethernet device comprises a plurality of Management Data Input/Output (MDIO) Manageable Device (MMD) registers storing Ethernet register field definitions that operate a management interface to one or more MMD devices. An MDIO controller, communicatively coupled to the plurality of MMD registers can control communication via the management interface to the one or more MMD devices based on a mapping of the set of Ethernet register field definitions to the plurality of MMD registers, and dynamically modify the mapping of the set of Ethernet register field definitions to the plurality of MMD registers.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: Eric Mouchel La Fosse, Paul Louis Chazhoor, Chee Kiang Goh, Hak Keong Sim
  • Publication number: 20200162406
    Abstract: Examples include a method of identifying single twisted pair cable Ethernet auto-negotiation requests or double twisted pair cables Ethernet auto-negotiation requests using detection of message time interval patterns. The method includes receiving, by a first Ethernet device, a plurality of messages transmitted by a second Ethernet device over a single twisted pair cable connecting the first Ethernet device and the second Ethernet device; storing one or more time intervals between starting times of successive pairs of the plurality of messages; determining if a pattern is found in the time intervals; when the pattern is found, setting a single twisted pair cable communications mode between the first Ethernet device and the second Ethernet device; and performing priority resolution between the first Ethernet device and the second Ethernet device.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 21, 2020
    Inventors: Chee-kiang GOH, Mario TRAEBER
  • Publication number: 20190052306
    Abstract: A device comprises a clock source configured to provide a spread-spectrum modulated clock signal and a control signal associated with the spread-spectrum modulated clock signal. The device also comprises a circuitry configured to receive the spread-spectrum modulated clock signal, to receive the control signal, and to sample a data signal in accordance with the spread-spectrum modulated clock signal and the control signal.
    Type: Application
    Filed: August 10, 2017
    Publication date: February 14, 2019
    Inventors: Chee Kiang Goh, Mario Traeber
  • Publication number: 20080008255
    Abstract: A discrete multitone (DMT) transceiver communicates with multiple channels generates and receives DMT symbols each having a duration of a timeslot. A transmitter portion of the transceiver includes a symbol processor which generates symbols for multiple channels sequentially, and stores the generated symbols in a buffer until they are transmitted. A receiver portion simultaneously receives symbols on multiple channels and stores the symbols in a buffer, from which the symbols on different channels are read and processed sequentially. To reduce the rate of communication on a given channel, the symbol processors may be idle in respect of some of the timeslots corresponding to that channel. The transceiver may alternatively be an OFDM transceiver.
    Type: Application
    Filed: July 10, 2006
    Publication date: January 10, 2008
    Inventors: Raj Kumar Jain, Pinxing Lin, Hak Keong Sim, Chee Kiang Goh