Patents by Inventor Chee-Kong Ung

Chee-Kong Ung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device
    Patent number: 10581414
    Abstract: A semiconductor integrated circuit device includes a chip main circuit, a damper and a passive component. The chip main circuit is coupled to a power source and performs a predetermined function. The damper is coupled to an output terminal of the chip main circuit. The passive component is coupled to the chip main circuit via the damper.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: March 3, 2020
    Assignee: MediaTek Inc.
    Inventors: Chun-Neng Liao, Meng-Hsin Chiang, Chun-Wei Chang, Chee-Kong Ung, Ching-Chih Li
  • POWER MANAGEMENT CIRCUIT AND ASSOCIATED POWER MANAGEMENT METHOD
    Publication number: 20170300077
    Abstract: A power management circuit includes a voltage sensing circuit and a supply voltage adjusting circuit. The voltage sensing circuit is arranged for sensing a plurality of voltages respectively of a plurality of nodes of a PCB to generate a sensing result. The supply voltage adjusting circuit is coupled to the voltage sensing circuit, and is arranged for determining a voltage level of a supply voltage supplied to a power plane of the PCB by referring to the sensing result.
    Type: Application
    Filed: July 4, 2017
    Publication date: October 19, 2017
    Inventors: Chia-Tao Hsu, Chee-Kong Ung, Li-Chun Yang, Yu-Sung Chen, Ming-Tse Dai
  • Power management circuit and associated power management method
    Patent number: 9733661
    Abstract: A power management circuit includes a voltage sensing circuit and a supply voltage adjusting circuit. The voltage sensing circuit is arranged for sensing a plurality of voltages respectively of a plurality of nodes of a PCB to generate a sensing result. The supply voltage adjusting circuit is coupled to the voltage sensing circuit, and is arranged for determining a voltage level of a supply voltage supplied to a power plane of the PCB by referring to the sensing result.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: August 15, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chia-Tao Hsu, Chee-Kong Ung, Li-Chun Yang, Yu-Sung Chen, Ming-Tse Dai
  • Microelectronic package with surface mounted passive element
    Patent number: 9660017
    Abstract: A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 23, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chao-Yang Yeh, Chee-Kong Ung, Tzu-Hung Lin, Jia-Wei Fang
  • SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    Publication number: 20170111032
    Abstract: A semiconductor integrated circuit device includes a chip main circuit, a damper and a passive component. The chip main circuit is coupled to a power source and performs a predetermined function. The damper is coupled to an output terminal of the chip main circuit. The passive component is coupled to the chip main circuit via the damper.
    Type: Application
    Filed: September 23, 2016
    Publication date: April 20, 2017
    Inventors: Chun-Neng LIAO, Meng-Hsin CHIANG, Chun-Wei CHANG, Chee-Kong UNG, Ching-Chih LI
  • MICROELECTRONIC PACKAGE WITH SURFACE MOUNTED PASSIVE ELEMENT
    Publication number: 20160211318
    Abstract: A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.
    Type: Application
    Filed: October 29, 2015
    Publication date: July 21, 2016
    Inventors: Chao-Yang Yeh, Chee-Kong Ung, Tzu-Hung Lin, Jia-Wei Fang
  • POWER MANAGEMENT CIRCUIT AND ASSOCIATED POWER MANAGEMENT METHOD
    Publication number: 20160091915
    Abstract: A power management circuit includes a voltage sensing circuit and a supply voltage adjusting circuit. The voltage sensing circuit is arranged for sensing a plurality of voltages respectively of a plurality of nodes of a PCB to generate a sensing result. The supply voltage adjusting circuit is coupled to the voltage sensing circuit, and is arranged for determining a voltage level of a supply voltage supplied to a power plane of the PCB by referring to the sensing result.
    Type: Application
    Filed: September 29, 2014
    Publication date: March 31, 2016
    Inventors: Chia-Tao Hsu, Chee-Kong Ung, Li-Chun Yang, Yu-Sung Chen, Ming-Tse Dai