Patents by Inventor Chee Liau

Chee Liau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050216246
    Abstract: A device characterization concept to test a semiconductor design by simulation includes storing a defined pattern and defined pattern analysis length, an analysis time and a defined number of characterization design parameters as a list in a memory simulating a device under test (DUT). The design parameters are a function of different customer-like pattern and test conditions according to the equation characterize design parameters (randomize/optimize (input pattern, test condition)) by using a pattern and condition variation and optimization technique (PCVOT), so that the design parameters are a function of different customer-like pattern and test conditions and that the range of design parameters variation with respect to the different input pattern or condition or combination of them is analyzed until the worst case is detected.
    Type: Application
    Filed: March 15, 2005
    Publication date: September 29, 2005
    Inventor: Chee Liau