Abstract: Methods, apparatus, and systems to dynamically schedule a workload to among compute blocks based on temperature are disclosed. An apparatus to schedule a workload to at least one of a plurality of compute blocks based on temperature includes a prediction engine to determine (i) a first predicted temperature of a first compute block of the plurality of compute blocks and (ii) a second predicted temperature of a second compute block of the plurality of compute blocks. The apparatus also includes a selector to select between the first compute block and the second compute block for assignment of the workload. The selection is based on which of the first and second predicted temperatures is lower. The apparatus further includes a workload scheduler to assign the workload to the selected one of the first or second compute blocks.

Abstract: Three components are used to adjust the CPU peak power based on the USB TYPE-C device states. These components include operating system (OS) Peak Power Manager, USB TYPE-C Connector Manager, and USB TYPE-C Protocol Device Driver. The USB TYPE-C Connector Manager sends a synchronous request to the OS Peak Power Manager when a USB TYPE-C power sink device is attached or detached, and the USB TYPE-C Protocol Device Driver sends a synchronous request to the Peak Power Manager when the power sink transitions device state. The Peak Power Manager takes power budget from the CPU when the USB TYPE-C connector is attached to a power sink and is active (e.g., high power device state), and gives back the power budget to the CPU for performance when the USB TYPE-C connector is either detached or the attached and power sink device is idle (lowest device state).

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to improve computing device power management. An example apparatus includes a usage classifier to classify usage of a computing system, a low battery probability determiner to determine a probability of the computing system operating with a low battery capacity based on the classification, a policy reward determiner to determine an adjustment of a policy based on at least one of the classification or the probability, and determine a battery capacity of the computing system in response to the adjustment, and a policy adjustor to adjust the policy in response to the battery capacity satisfying a threshold.

Abstract: Apparatus and methods for managing power consumption of a data-path in a computer system are provided, the data-path comprising a first port and a second port, the first port comprising a high-speed and the second port comprising a low-speed port. The disclosed method including connecting a device to the data-path, determining that the connected device is to communicate using the second port and turning off an active circuit associated with the first port of the data-path.

Abstract: Described are mechanisms and methods for implementing highly configurable power delivery management policies. An apparatus may comprise a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may include a memory to store a first table having one or more first entries and to store a second table having one or more respectively corresponding second entries. The second circuitry may, upon the occurrence of an event, test a condition specified by an entry in the first table. The third circuitry may, upon the test of the condition having a positive result, evaluate a set of one or more parameters as specified by an entry in a second table corresponding with the entry in the first table. The fourth circuitry may initiate a power-management action based upon the evaluation of the set of one or more parameters.

Abstract: A hardware and/or software (e.g., a controller and/or firmware or software) that monitors a remaining capacity of a battery and adjusts a continuum of system performance settings ranging from best performance to best energy efficiency. The controller starts with best performance setting (at the expense of energy efficiency), and then the controller gradually shifts toward energy efficiency setting (at the expense of performance) when a battery usage exceeds a pre-defined drain rate (e.g., there is a deficit in the battery remaining capacity until the next charge). The controller reverts from energy efficiency setting towards high performance setting when the battery drain rate or discharge rate slows down (e.g., there is a surplus in the battery remaining capacity until the next charge).

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

Abstract: In some examples, an apparatus includes a battery and a dynamic voltage source coupled in series with the battery. The dynamic voltage source is to maintain (or clamp) a system voltage from going below a minimum system voltage.

Abstract: Techniques are provided for operating a computing system in a peak power mode while avoiding increased degradation of a battery. The peak power mode include cycles with peak and off-peak currents. The amplitude and duration of the peak and off-peak currents are governed by a thermal/heat budget of the battery. A processor can read the battery information during usage and calculate one or more parameters which are derived from heat. If a parameter is smaller than a reference value, the processor can update the peak power parameters to provide an increase in peak current/power and/or duration. If a parameter is larger than the reference value, no heat budget is available to provide an increase in peak current/power and/or duration. The thermal/heat budget can be enforced over each cycle of the peak power mode or in a summation over multiple cycles.

Abstract: Peak power setting circuitry is provided to set a peak power value for an integrated circuit device. A power supply interface is to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device and processing circuitry is provided to calculate an approximate peak power for the integrated circuit device. A peak power for the integrated circuit device is determined by increasing the approximate peak power depending on an amount by which the integrated circuit device power is reduced in response to assertion of a throttling signal.

Abstract: Described is an apparatus and method to prevent a processor from abruptly shutting down by proactive power management. The apparatus comprises a power supply rail to receive a current and a voltage from a power supply generator (e.g., a DC-DC converter, and low dropout regulator); a processor coupled to the power supply rail, wherein the processor is to operate with a current and a voltage provided by the power supply rail; and an interface to receive a request to throttle one or more performance parameters of the processor when a monitored current through the power supply rail or a monitored voltage on the power supply rail crosses a threshold current or a threshold voltage, respectively, wherein the threshold current is below a catastrophic threshold current of a voltage regulator, or wherein the threshold voltage is above a catastrophic threshold voltage of the processor.

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

Abstract: A software and/or hardware to monitor system usage including how long system ran on a battery or with an AC adapter. The software and/or hardware judges whether fast charging is needed and/or how much charge is needed, and optimizes battery charging settings.

Abstract: A first circuit to receive from a sensor a thermal condition of a voltage regulator while circuitry comprising the voltage regulator is to regulate delivery of power to a power domain having first and second components. The circuitry is to control a first power consumption rate of the first component based on a first parameter and control a second power consumption rate of the second component based on a second parameter. The first circuit monitors the thermal condition and generates an evaluation result based on a test criterion. A second circuit receives from the first circuit a signal based on the evaluation result. Based on the signal, the second circuit is to signal the circuitry to change the first parameter. An amount of any change to the second parameter based on the evaluation result is different than an amount of change to the first parameter based on the evaluation result.

Abstract: A driver (e.g., a firmware or software) that improves the performance of the system-on-chip (SoC) in battery mode. The driver is a Peak Power Manager (PPM) which allows drastically higher SoC peak power limit levels (and thus higher Turbo performance) in battery mode. The PPM sets the Vth threshold voltage (the voltage level at which the platform will throttle the SoC) in such a way as to prevent the system from unexpected shutdown (or black screening). The PPM calculates the Psoc,pk SoC Peak Power Limit (e.g., PL4), according to the threshold voltage (Vth). These are two dependent parameters, if one is set, the other can be calculated. The scheme by the PPM is used to optimally set one parameter (Vth) based on the system parameters, and the history of the operation.

Abstract: When power is provided through a USB-C cable from a source device to a sink device, a sudden connection or disconnection of the cable between the two devices may cause a sudden power surge or power drop in at least one of those devices, leading to other problems. To avoid this sudden event from causing potential damage or disruption to one of the devices, in some embodiments a CC pin in the cable is used to announce the impending connection/disconnection, and the device may throttle back its power consumption before power is actually applied to or removed from the power pins.

Abstract: Described are mechanisms and methods for implementing highly configurable power delivery management policies. An apparatus may comprise a first circuitry, a second circuitry, a third circuitry, and a fourth circuitry. The first circuitry may include a memory to store a first table having one or more first entries and to store a second table having one or more respectively corresponding second entries. The second circuitry may, upon the occurrence of an event, test a condition specified by an entry in the first table. The third circuitry may, upon the test of the condition having a positive result, evaluate a set of one or more parameters as specified by an entry in a second table corresponding with the entry in the first table. The fourth circuitry may initiate a power-management action based upon the evaluation of the set of one or more parameters.

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.