Patents by Inventor Chee Ming Lam

Chee Ming Lam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power semiconductor device with dual heat dissipation structures
    Patent number: 12334414
    Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to a pad at the second side of the semiconductor die; and a molding compound encapsulating the die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.
    Type: Grant
    Filed: January 8, 2024
    Date of Patent: June 17, 2025
    Assignee: Infineon Technologies AG
    Inventors: Jayaganasan Narayanasamy, Angel Enverga, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
  • SEMICONDUCTOR PACKAGE AND RELATED METHODS OF MANUFACTURING
    Publication number: 20240145340
    Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to a pad at the second side of the semiconductor die; and a molding compound encapsulating the die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Inventors: Jayaganasan Narayanasamy, Angel Enverge, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
  • Power semiconductor device with dual heat dissipation structures
    Patent number: 11908771
    Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: February 20, 2024
    Assignee: Infineon Technologies AG
    Inventors: Jayaganasan Narayanasamy, Angel Enverga, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
  • DUAL FUNCTIONAL THERMAL PERFORMANCE SEMICONDUCTOR PACKAGE AND RELATED METHODS OF MANUFACTURING
    Publication number: 20230154827
    Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.
    Type: Application
    Filed: November 12, 2021
    Publication date: May 18, 2023
    Inventors: Jayaganasan Narayanasamy, Angel Enverga, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
  • Package lead design with grooves for improved dambar separation
    Patent number: 11362023
    Abstract: A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: June 14, 2022
    Assignee: Infineon Technologies AG
    Inventors: Jayaganasan Narayanasamy, Meng How Chong, Elmer Senorin Holgado, Chee Ming Lam, Sanjay Kumar Murugan, Arivindran Navaretnasinggam, Kai Yang Tan, Lee Shuang Wang
  • POWER SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING A POWER SEMICONDUCTOR PACKAGE
    Publication number: 20220115245
    Abstract: A method for fabricating a power semiconductor package includes: providing a leadframe having a die pad and a frame, wherein the die pad is connected to the frame by at least one tie bar; attaching a semiconductor die to the die pad; laser cutting through the at least one tie bar, thereby forming a cut surface; and after the laser cutting, molding over the die pad and the semiconductor die, wherein the cut surface is completely covered by molding compound.
    Type: Application
    Filed: October 4, 2021
    Publication date: April 14, 2022
    Inventors: Jayaganasan Narayanasamy, Syahir Abd Hamid, Meng How Chong, Michael Reyes Godoy, Chee Ming Lam, Adbul Rahman Mohamed, Sanjay Kumar Murugan, Thomas Stoek
  • Package Lead Design with Grooves for Improved Dambar Separation
    Publication number: 20210013135
    Abstract: A lead frame includes a die pad, a first lead extending away from the die pad, a peripheral structure mechanically connected to the first lead and the die pad, and a first groove in an outer surface of the first lead. The first groove extends longitudinally along the first lead away from the die pad.
    Type: Application
    Filed: July 12, 2019
    Publication date: January 14, 2021
    Inventors: Jayaganasan Narayanasamy, Meng How Chong, Elmer Senorin Holgado, Chee Ming Lam, Sanjay Kumar Murugan, Arivindran Navaretnasinggam, Kai Yang Tan, Lee Shuang Wang