Abstract: A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.

Abstract: A semiconductor device substrate is provided. The substrate includes an embedded trace substrate (ETS) portion. The ETS portion includes a first conductive layer embedded in the ETS portion at a first major surface. A portion of the first conductive layer is patterned to form a signal line. A non-conductive layer is disposed between the first conductive layer and a second conductive layer second embedded in the ETS portion. A third conductive layer is formed over the first major surface of the ETS portion. The third conductive layer is configured to form a stripline with the signal line of the first conductive layer.

Abstract: A semiconductor device substrate is provided. The substrate includes an embedded trace substrate (ETS) portion. The ETS portion includes a first conductive layer embedded in the ETS portion at a first major surface. A portion of the first conductive layer is patterned to form a signal line. A non-conductive layer is disposed between the first conductive layer and a second conductive layer second embedded in the ETS portion. A third conductive layer is formed over the first major surface of the ETS portion. The third conductive layer is configured to form a stripline with the signal line of the first conductive layer.

Abstract: There is disclosed a semiconductor package assembly comprising: a substrate having a top substrate surface and a substrate bottom surface; a first semiconductor die, partially over the substrate and having a die bottom surface having first and second pluralities of I/O pads thereon; a first plurality of localised electrical connection components (LECCs), affixed between the die bottom surface and the substrate top surface and providing electrical connections between the substrate and the first plurality of I/O pads; a second plurality of LECCs, affixed to the substrate bottom surface, and for providing electrical connection between the substrate and a circuit board; wherein the second plurality of I/O pads are arranged for providing electrical connections to a chip-scale-package unit to be affixed to the first semiconductor die by a third plurality of LECCs, and to be positioned in a same horizonal plane as the substrate. Corresponding methods are also disclosed.

Abstract: A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.

Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.

Abstract: A semiconductor device substrate is provided. The substrate includes an embedded trace substrate (ETS) portion. The ETS portion includes a first conductive layer embedded in the ETS portion at a first major surface. A portion of the first conductive layer is patterned to form a signal line. A non-conductive layer is disposed between the first conductive layer and a second conductive layer second embedded in the ETS portion. A third conductive layer is formed over the first major surface of the ETS portion. The third conductive layer is configured to form a stripline with the signal line of the first conductive layer.

Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.

Abstract: Embodiments are provided herein for a substrate having one or more embedded traces and a method for fabricating one or more embedded traces. The method includes: forming a bump on a first major surface of a substrate, the bump having a height measured from the first major surface to a top surface of the bump; forming a trace comprising: a lower trace portion that directly contacts the first major surface, a sidewall trace portion that directly contacts at least one sidewall of the bump, and an upper trace portion that directly contacts the top surface of the bump; depositing a blanket dielectric layer over the trace; and etching away a top portion of the blanket dielectric layer to expose a top surface of the upper trace portion.

Abstract: Embodiments for a packaged semiconductor device and methods of making are provided herein, which includes a packaged semiconductor device including: a semiconductor die; a carrier; a plurality of electrical connections formed between the semiconductor die and the carrier; an electrical isolation layer that covers an outer surface of each of the plurality of electrical connections; and a conductive underfill structure between the semiconductor die and the carrier, and surrounding each of the plurality of electrical connections, wherein the electrical isolation layer electrically isolates each electrical connection from the conductive underfill structure.

Abstract: A microscale selective laser sintering (?-SLS) that improves the minimum feature-size resolution of metal additively manufactured parts by up to two orders of magnitude, while still maintaining the throughput of traditional additive manufacturing processes. The microscale selective laser sintering includes, in some embodiments, ultra-fast lasers, a micro-mirror based optical system, nanoscale powders, and a precision spreader mechanism. The micro-SLS system is capable of achieving build rates of at least 1 cm3/hr while achieving a feature-size resolution of approximately 1 ?m. In some embodiments, the exemplified systems and methods facilitate a direct write, microscale selective laser sintering ?-SLS system that is configured to write 3D metal structures having features sizes down to approximately 1 ?m scale on rigid or flexible substrates. The exemplified systems and methods may operate on a variety of material including, for example, polymers, dielectrics, semiconductors, and metals.

Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.

Abstract: Embodiments are provided herein for a substrate having one or more embedded traces and a method for fabricating one or more embedded traces. The method includes: forming a bump on a first major surface of a substrate, the bump having a height measured from the first major surface to a top surface of the bump; forming a trace comprising: a lower trace portion that directly contacts the first major surface, a sidewall trace portion that directly contacts at least one sidewall of the bump, and an upper trace portion that directly contacts the top surface of the bump; depositing a blanket dielectric layer over the trace; and etching away a top portion of the blanket dielectric layer to expose a top surface of the upper trace portion.

Abstract: Embodiments of a substrate are provided herein, which include: a first metal plane and a second metal plane in a first metal layer, the first and second metal planes laterally separated by a first gap of dielectric material; and a third metal plane and a fourth metal plane in a second metal layer vertically adjacent to the first metal layer, the third and fourth metal planes laterally separated by a second gap of dielectric material, wherein the second gap comprises a first laterally-shifted gap portion and a second laterally-shifted gap portion, the first laterally-shifted gap portion is laterally offset from a vertical footprint of the first gap in a first lateral direction, and the second laterally-shifted gap portion is laterally offset from the vertical footprint of the first gap in a second lateral direction opposite the first lateral direction.

Abstract: A method of manufacturing a hybrid package including a flat package and a Wafer Level Chip Scale Package (WLCSP) is disclosed. The method includes fabricating a strip including a plurality of flat packages attached to each other via metal pins, turning the strip upside down, applying a layer of a thermal interface material (TIM) on each of the flat packages while the each of the flat packages is turned upside down, mounting the WLCSP on the layer of the TIM such that a top side of the WLCSP is interfaced with the layer of the TIM, curing the layer of the TIM and singulating each of the flat packages by cutting the metal pins and bending the metal pins.

Abstract: A “universal” substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.

Abstract: A method of making a packaged integrated circuit device includes forming a lead frame with leads that have an inner portion and an outer portion, the inner portion of the lead is between a periphery of a die pad and extends to one end of openings around the die pad. The outer portion of the leads are separated along their length almost up to an opposite end of the openings. Leads in a first subset of the leads alternate with leads in a second subset of the leads. The inner portion of the first subset of the leads is bent. The die pad, the inner portion of the leads, and only a first portion of the openings adjacent the inner portion of the leads are encapsulated. A second portion of the openings and the output portions of the leads form a dam bar for the encapsulating material.

Abstract: A “universal” substrate for a semiconductor device is formed of a non-conductive substrate material. A uniform array of conductive pillars is formed in the substrate material. The pillars extend from a top surface of the substrate material to a bottom surface of the substrate material. A die flag may be formed on the top surface of the substrate material. Pillars underneath the die flag are connected to pillars beyond a perimeter of the die flag with wires. Power and ground rings may be formed by connecting rows of pillars that surround the die flag.

Abstract: Embodiments of a microelectronic packaged device and methods of making are provided, where the microelectronic packaged device includes a system package comprising a first die and a second die, wherein the first die and the second die are laterally positioned to one another, and the first die and the second die are laterally separated from one another by mold compound; and a conductive trace formed between a first conductive surface on an exposed surface of the first die and a second conductive surface on an exposed surface of the second die, wherein the conductive trace is laser sintered directly on the first conductive surface, on a portion of the exposed surface of the first die, on a portion of a top surface of the mold compound, on a portion of the exposed surface of the second die, and on the second conductive surface.

Abstract: A microscale selective laser sintering (?-SLS) that improves the minimum feature-size resolution of metal additively manufactured parts by up to two orders of magnitude, while still maintaining the throughput of traditional additive manufacturing processes. The microscale selective laser sintering includes, in some embodiments, ultra-fast lasers, a micro-mirror based optical system, nanoscale powders, and a precision spreader mechanism. The micro-SLS system is capable of achieving build rates of at least 1 cm3/hr while achieving a feature-size resolution of approximately 1 ?m. In some embodiments, the exemplified systems and methods facilitate a direct write, microscale selective laser sintering ?-SLS system that is configured to write 3D metal structures having features sizes down to approximately 1 ?m scale on rigid or flexible substrates. The exemplified systems and methods may operate on a variety of material including, for example, polymers, dielectrics, semiconductors, and metals.