Patents by Inventor Chee Seng Leong
Chee Seng Leong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230378061Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.Type: ApplicationFiled: April 20, 2023Publication date: November 23, 2023Inventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
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Patent number: 11670589Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.Type: GrantFiled: December 22, 2020Date of Patent: June 6, 2023Assignee: Intel CorporationInventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
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DEVICE, METHOD AND SYSTEM TO DETERMINE CALIBRATION INFORMATION WITH A SHARED RING OSCILLATOR CIRCUIT
Publication number: 20230088853Abstract: Techniques and mechanisms for determining calibration information based on tuning of a ring oscillator circuit formed with two integrated circuit (IC) dies. In an embodiment, an oscillator circuit comprises an in-series arrangement of delay circuits including a first one or more delay circuits of a first die, and a second one or more delay circuits of a second die. Respective circuitry of the first die and the second die performs tuning to match an oscillation frequency of the oscillator circuit with a reference frequency. An operational setting of the tuned oscillator circuit is provided to calibrate transmitter circuitry of the first die and the second die. In another embodiment, tuning of the oscillator circuit is further based on tuning of a local oscillator circuit of one of the first die or the second die.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: Intel CorporationInventor: Chee Seng Leong -
Patent number: 11043942Abstract: A variable delay circuit includes first pull-up and first pull-down current paths and second pull-up and second pull-down current paths. The variable delay circuit generates first delays in an output signal relative to an input signal in response to the first pull-up and first pull-down current paths being enabled by a first control signal. The variable delay circuit generates second delays in the output signal relative to the input signal that are different than the first delays in response to the second pull-up and second pull-down current paths being enabled by a second control signal.Type: GrantFiled: December 8, 2017Date of Patent: June 22, 2021Assignee: Intel CorporationInventor: Chee Seng Leong
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Publication number: 20210111116Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.Type: ApplicationFiled: December 22, 2020Publication date: April 15, 2021Inventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
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Patent number: 10886218Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.Type: GrantFiled: June 28, 2019Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
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Patent number: 10848155Abstract: A multichip package may include a transmitter die and a receiver mounted on a substrate. The transmitter die may be coupled to the receiver die through die-to-die connections such as microbumps and conductive paths in the substrate. The transmitter die may include flexible transmitter circuitry having transceiver logic and driver circuitry. The driver circuitry may include a high-swing driver and a low-swing driver optionally equalization circuitry. The driver circuitry may operable in a high-swing mode, a low-swing mode with equalization, and a low-swing mode without equalization. Transmitter circuitry provided in this way removes undesirable DC voltage paths to ground present in other driving schemes to reduce power consumption while still meeting bandwidth, flexibility, and scalability demands.Type: GrantFiled: February 15, 2019Date of Patent: November 24, 2020Assignee: Intel CorporationInventor: Chee Seng Leong
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Publication number: 20190326210Abstract: The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.Type: ApplicationFiled: June 28, 2019Publication date: October 24, 2019Inventors: Chee Hak Teh, Chee Seng Leong, Lai Guan Tang, Han Wooi Lim, Hee Kong Phoon
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Patent number: 10333504Abstract: Described is an apparatus which comprises: a sensor to detect entrance of single-ended-zero (SE0) state on first and second data lines, and to detect exit of the SE0 state; and a clamp unit to clamp an overshoot or undershoot condition on the first or second data lines during the detected entrance and exit of the SE0 state.Type: GrantFiled: November 26, 2013Date of Patent: June 25, 2019Assignee: INTEL CORPORATIONInventors: Amit Kumar Srivastava, Chee Seng Leong
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Publication number: 20190181865Abstract: A multichip package may include a transmitter die and a receiver mounted on a substrate. The transmitter die may be coupled to the receiver die through die-to-die connections such as microbumps and conductive paths in the substrate. The transmitter die may include flexible transmitter circuitry having transceiver logic and driver circuitry. The driver circuitry may include a high-swing driver and a low-swing driver optionally equalization circuitry. The driver circuitry may operable in a high-swing mode, a low-swing mode with equalization, and a low-swing mode without equalization. Transmitter circuitry provided in this way removes undesirable DC voltage paths to ground present in other driving schemes to reduce power consumption while still meeting bandwidth, flexibility, and scalability demands.Type: ApplicationFiled: February 15, 2019Publication date: June 13, 2019Applicant: Intel CorporationInventor: Chee Seng Leong
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Publication number: 20190123727Abstract: A variable delay circuit includes first pull-up and first pull-down current paths and second pull-up and second pull-down current paths. The variable delay circuit generates first delays in an output signal relative to an input signal in response to the first pull-up and first pull-down current paths being enabled by a first control signal. The variable delay circuit generates second delays in the output signal relative to the input signal that are different than the first delays in response to the second pull-up and second pull-down current paths being enabled by a second control signal.Type: ApplicationFiled: December 8, 2017Publication date: April 25, 2019Applicant: Intel CorporationInventor: Chee Seng Leong
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Patent number: 10200046Abstract: A delay-locked loop includes multiple inverters coupled together, wherein the inverters receive an input clock signal and output a first clock signal and a second clock signal. The input clock signal passes through a first set of inverters having a first number of inverters to generate the first clock signal. The input clock signal also passes through a second set of inverters having a second number of inverters one inverter greater than the first number of inverters to generate the second clock signal. The delay-locked loop also includes a polarity matching block that receives the first clock signal and the second clock signal and changes polarity of one of the first clock signal and the second clock signal.Type: GrantFiled: February 15, 2017Date of Patent: February 5, 2019Assignee: Intel CorporationInventors: Chee Seng Leong, Tat Hin Tan
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Patent number: 9941890Abstract: An integrated circuit with a phase-locked loop (PLL) is provided. The PLL may include a phase frequency detector, a charge pump, a source follower circuit, a variable oscillator, a frequency divider, and a control block. The phase frequency detector may be configured to align or lock a feedback clock signal to a reference clock signal. The control block includes clock loss detection circuits that are used to determine whether the reference clock signal or the feedback clock signal has stopped toggling. In response to detecting a clock loss event for either the reference or the feedback clock signal, the control block may disable the phase frequency detector to place the charge pump in a tristate mode and may apply a predetermined bias voltage to the source follower circuit to help minimize electrical overstress.Type: GrantFiled: June 20, 2016Date of Patent: April 10, 2018Assignee: Altera CorporationInventor: Chee Seng Leong
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Publication number: 20170366190Abstract: An integrated circuit with a phase-locked loop (PLL) is provided. The PLL may include a phase frequency detector, a charge pump, a source follower circuit, a variable oscillator, a frequency divider, and a control block. The phase frequency detector may be configured to align or lock a feedback clock signal to a reference clock signal. The control block includes clock loss detection circuits that are used to determine whether the reference clock signal or the feedback clock signal has stopped toggling. In response to detecting a clock loss event for either the reference or the feedback clock signal, the control block may disable the phase frequency detector to place the charge pump in a tristate mode and may apply a predetermined bias voltage to the source follower circuit to help minimize electrical overstress.Type: ApplicationFiled: June 20, 2016Publication date: December 21, 2017Inventor: Chee Seng Leong
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Patent number: 9813064Abstract: Described is an apparatus which comprises: a first power supply; a second power supply lower than the first power supply; first and second transistors coupled in series and to be biased, the first and second transistors coupled to a pad; a first pull-up transistor coupled to the first power supply and to one of the first or second transistors; a pull-down transistor coupled to one of the first or second transistors; and a second pull-up transistor coupled to the second power supply, the pull-down transistor, and to one of the first or second transistors.Type: GrantFiled: December 17, 2013Date of Patent: November 7, 2017Assignee: Intel CorporationInventors: Chia How Low, Chee Seng Leong, Yick Yaw Ho
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Publication number: 20160233854Abstract: Described is an apparatus which comprises: a sensor to detect entrance of single-ended-zero (SE0) state on first and second data lines, and to detect exit of the SE0 state; and a clamp unit to clamp an overshoot or undershoot condition on the first or second data lines during the detected entrance and exit of the SE0 state.Type: ApplicationFiled: November 26, 2013Publication date: August 11, 2016Applicant: Intel CorporationInventors: Amit Kumar SRIVASTAVA, Chee Seng LEONG
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Publication number: 20150171830Abstract: Described is an apparatus which comprises: a first power supply; a second power supply lower than the first power supply; first and second transistors coupled in series and to be biased, the first and second transistors coupled to a pad; a first pull-up transistor coupled to the first power supply and to one of the first or second transistors; a pull-down transistor coupled to one of the first or second transistors; and a second pull-up transistor coupled to the second power supply, the pull-down transistor, and to one of the first or second transistors.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Inventors: Chia How LOW, Chee Seng LEONG, Yick Yaw HO
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Patent number: 8912447Abstract: A method includes patterning one or more electrical layers on a substrate; shaping the patterned substrate into a 3-dimensional contour, wherein the contour including a significant change in gradient in or adjacent to one or more sensing areas of the electrical layer, and over-molding the shaped substrate. Degradation of a trace in the electrical layer at or adjacent to the one or more sensing areas during shaping and/or over-molding is substantially minimized based on the width of the trace, the thickness or number of layers of the trace, the bending radius of the trace, the material of the trace, and/or a primer over layer on the trace.Type: GrantFiled: October 9, 2012Date of Patent: December 16, 2014Assignee: Fischer Technology Pte. Ltd.Inventors: Chee Seng Leong, Sze Lam Chua
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Publication number: 20140036428Abstract: A method comprising: patterning one or more electrical layers on a substrate; shaping the patterned substrate into a 3-dimensional contour, wherein the contour including a significant change in gradient in or adjacent to one or more sensing areas of the electrical layer, and over-moulding the shaped substrate, wherein degradation of a trace in the electrical layer at or adjacent to the one or more sensing areas during shaping and/or over-moulding is substantially minimised based on the width of the trace, the thickness or number of layers of the trace, the bending radius of the trace, the material of the trace, and/or a primer over layer on the trace.Type: ApplicationFiled: October 9, 2012Publication date: February 6, 2014Applicant: Fischer Technology Pte LtdInventors: Chee Seng Leong, Sze Lam Chua