Patents by Inventor Chee-Seng Tan
Chee-Seng Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11280506Abstract: An air-conditioner unit comprising: a temperature regulation unit having an evaporator; a condensate filtration unit arranged to receive a condensate from the evaporator, and operable to filter the condensate; wherein the air-conditioner unit comprises a controller to operate the condensate filtration unit between a plurality of purging states, the plurality of purging states comprises a first purging state wherein the condensate is purged bypassing the condensate filter unit and a second purging state wherein filtered condensate is purged.Type: GrantFiled: July 10, 2017Date of Patent: March 22, 2022Assignee: TRENDS HOME ELECTRICAL PTE. LTD.Inventors: Wee Teck Ho, Tiau Kai Tay, Chee Seng Tan
-
Patent number: 11190335Abstract: A method for performing pattern detection and alignment on a programmable logic device is disclosed. A word aligner unit, implemented by a hard intellectual property block, is configured to detect a plurality of control characters by recognizing a proper subset of bits that are common among the plurality of control characters. It is determined whether a predetermined number of consecutive control characters has been detected in a frame of data. A boundary location associated with a detected predetermined number of consecutive control characters from the word aligner unit is identified. The frame of data is aligned in response to the boundary location associated with the detected predetermined number of consecutive control characters.Type: GrantFiled: January 23, 2018Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Boon Hong Oh, Ivan Fu Sun Teh, Chee Seng Tan
-
Patent number: 10958411Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.Type: GrantFiled: April 6, 2020Date of Patent: March 23, 2021Assignee: Altera CorporationInventors: Boon Hong Oh, Chee Seng Tan, Chau Perng Chin
-
Publication number: 20200235906Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.Type: ApplicationFiled: April 6, 2020Publication date: July 23, 2020Inventors: Boon Hong Oh, Chee Seng Tan, Chau Perng Chin
-
Patent number: 10615955Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.Type: GrantFiled: October 8, 2018Date of Patent: April 7, 2020Assignee: Altera CorporationInventors: Boon Hong Oh, Chee Seng Tan, Chau Perng Chin
-
Publication number: 20190316793Abstract: An air-conditioner unit comprising: a temperature regulation unit having an evaporator; a condensate filtration unit arranged to receive a condensate from the evaporator, and operable to filter the condensate; wherein the air-conditioner unit comprises a controller to operate the condensate filtration unit between a plurality of purging states, the plurality of purging states comprises a first purging state wherein the condensate is purged bypassing the condensate filter unit and a second purging state wherein filtered condensate is purged.Type: ApplicationFiled: July 10, 2017Publication date: October 17, 2019Applicant: TRENDS HOME ELECTRICAL PTE. LTD.Inventors: Wee Teck HO, Tiau Kai TAY, Chee Seng TAN
-
Publication number: 20190280850Abstract: A receiver circuit includes a transition density detector circuit that generates a transition density signal based on a comparison between a transition density of data words to a transition density threshold. The receiver circuit also includes a bit shift and pattern detector circuit that bit shifts one of the data words to generate bit shifted data in response to the transition density signal indicating that the transition density of the data words has reached the transition density threshold. The bit shift and pattern detector circuit counts a number of bits shifts performed on the bit shifted data to locate a synchronization character. The receiver circuit also includes a word alignment circuit that bit shifts the data words by the number of bits shifts to generate word aligned data.Type: ApplicationFiled: May 28, 2019Publication date: September 12, 2019Applicant: Intel CorporationInventors: Chee Seng Tan, Boon Hong Oh, Ivan Fu Sun Teh
-
Publication number: 20190044695Abstract: A method for performing pattern detection and alignment on a programmable logic device is disclosed. A word aligner unit, implemented by a hard intellectual property block, is configured to detect a plurality of control characters by recognizing a proper subset of bits that are common among the plurality of control characters. It is determined whether a predetermined number of consecutive control characters has been detected in a frame of data. A boundary location associated with a detected predetermined number of consecutive control characters from the word aligner unit is identified. The frame of data is aligned in response to the boundary location associated with the detected predetermined number of consecutive control characters.Type: ApplicationFiled: January 23, 2018Publication date: February 7, 2019Inventors: Boon Hong OH, Ivan Fu Sun TEH, Chee Seng TAN
-
Patent number: 10129013Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.Type: GrantFiled: January 25, 2017Date of Patent: November 13, 2018Assignee: Altera CorporationInventors: Boon Hong Oh, Chee Seng Tan, Chau Perng Chin
-
Patent number: 8183883Abstract: A memory configuration circuit is provided. The memory configuration circuit may be integrated into a programmable logic device (PLD) and as such, may be used to configure and reconfigure specific elements in the PLD. The memory configuration circuit includes a comparator circuit and a counter. The comparator circuit is coupled to receive two data words from two different memory configuration sources. The comparator circuit compares the two data words received before writing one of the data words to a configuration memory. One of the data words may be written to the configuration memory if the two data words compared are not equal. The counter increments the address of the memory configuration sources so that a next data word can be processed after the current data word is processed.Type: GrantFiled: April 16, 2010Date of Patent: May 22, 2012Assignee: Altera CorporationInventors: Chee Seng Tan, Chai Sia Tan, Elden Chau, John Tse, Neville Carvalho
-
Patent number: 7616181Abstract: A display adopting system-on-panel (SOP) design comprising a pixel array, a driving unit, a timing controller, and a first synchronization unit is provided. The pixel array is electrically connected with the driving unit. The timing controller generates a first set of timing signals to the driving unit. The first synchronization unit is set adjacent to an input of the driving unit for synchronizing the first set of timing signals.Type: GrantFiled: May 18, 2005Date of Patent: November 10, 2009Assignee: AU Optronics Corp.Inventors: Chun-Hung Kuo, Chee-Seng Tan, Wein-Town Sun
-
Publication number: 20060055692Abstract: A display adopting system-on-panel (SOP) design comprising a pixel array, a driving unit, a timing controller, and a first synchronization unit is provided. The pixel array is electrically connected with the driving unit. The timing controller generates a first set of timing signals to the driving unit. The first synchronization unit is set adjacent to an input of the driving unit for synchronizing the first set of timing signals.Type: ApplicationFiled: May 18, 2005Publication date: March 16, 2006Inventors: Chun-Hung Kuo, Chee-Seng Tan, Wein-Town Sun