Patents by Inventor Chee-Siang Ong

Chee-Siang Ong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9875973
    Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: January 23, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu, Wei Meng, Chee Siang Ong
  • Patent number: 9520365
    Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 13, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu, Wei Meng, Chee Siang Ong
  • Publication number: 20130241048
    Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.
    Type: Application
    Filed: April 30, 2013
    Publication date: September 19, 2013
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu, Wei Meng, Chee Siang Ong
  • Patent number: 8492203
    Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: July 23, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu, Wei Meng, Chee Siang Ong
  • Publication number: 20120187584
    Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.
    Type: Application
    Filed: June 20, 2011
    Publication date: July 26, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu, Wei Meng, Chee Siang Ong
  • Publication number: 20090042388
    Abstract: A semiconductor substrate is first provided. The semiconductor substrate includes a material layer and a patterned photoresist layer disposed on the material layer. Subsequently, a contact etching process is performed on the material layer by utilizing the patterned photoresist layer as an etching mask so to form an etched hole in the material layer. Thereafter, a solvent cleaning process is carried out on the semiconductor substrate by utilizing a cleaning solvent. Next, a water cleaning process is performed on the semiconductor substrate by utilizing deionized water. The temperature of the deionized water is in a range from 30° C. to 99° C.
    Type: Application
    Filed: August 10, 2007
    Publication date: February 12, 2009
    Inventors: Zhi-Qiang Sun, Tien-Cheng Lan, Hua-Kuo Lee, Jing-Hao Chen, Wen-Chun Huang, Run-Shun Wang, Jing-Ling Wang, Da-Jiang Yang, Chee-Siang Ong