Patents by Inventor Chee T. Chua

Chee T. Chua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process
    Patent number: 8161355
    Abstract: A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: April 17, 2012
    Assignee: MoSys, Inc.
    Inventors: Stephen Fung, Vithal Rao, Da-Guang Yu, J. Eric Ruetz, Chee T. Chua, Jawji Chen, Kameswara K. Rao
  • Two bits per cell non-volatile memory architecture
    Patent number: 8081521
    Abstract: A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: December 20, 2011
    Assignee: MoSys, Inc.
    Inventors: Chee T. Chua, Kameswara K. Rao, Vithal R. Rao, Jawji Chen, Da-Guang Yu, J. Eric Ruetz, Stephen Fung
  • Two Bits Per Cell Non-Volatile Memory Architecture
    Publication number: 20100208530
    Abstract: A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 19, 2010
    Applicant: MoSys, Inc.
    Inventors: Chee T. Chua, Kameswara K. Rao, Vithal R. Rao, Jawji Chen, Da-Guang Yu, J. Eric Ruetz, Stephen Fung
  • Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process
    Publication number: 20100205504
    Abstract: A method for selectively refreshing data in a nonvolatile memory array based on failure type detected by an error correction code. If the page is determined to be error-free, no refresh operation takes place. Otherwise, if single-error words on a page contain erased and programmed bit errors, then a refresh operation, consisting of an erase and program, takes place. The erase operation is skipped if single-error words on a page solely contain a program failure.
    Type: Application
    Filed: February 11, 2009
    Publication date: August 12, 2010
    Applicant: Mosys, Inc.
    Inventors: Stephen Fung, Vithal Rao, Da-Guang Yu, J. Eric Ruetz, Chee T. Chua, Jawji Chen, Kameswara K. Rao