Patents by Inventor Chee Wai Wong

Chee Wai Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LIPOSOMAL CORTICOSTEROIDS FOR TOPICAL INJECTION IN INFLAMED LESIONS OR AREAS
    Publication number: 20190151236
    Abstract: The invention relates to topical injection in inflamed lesions or areas with liposomal corticosteroids.
    Type: Application
    Filed: April 28, 2017
    Publication date: May 23, 2019
    Applicants: Enceladus Pharmaceuticals B.V., Universiteit Utrechat Holding B.V., Singapore Health Services PTE. LTD.
    Inventors: Josbert Maarten METSELAAR, Chee Wai WONG, Bertrand Marcel Stanislas CZARNY, Tina Tzee Ling WONG
  • Integrated circuit die configuration for packaging
    Patent number: 7714427
    Abstract: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package substrate in an angle with respect to a package substrate to point the corners of the die at the edges of the package substrate to reduce trace length outside the die. The center of the die may or may not coincide with the center of the substrate. In one embodiment, when compare to a centered, non-rotated die mounting position, mounting a die with corners pointing at the edges of the package substrate does not cause significant differences in substrate warpage.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: May 11, 2010
    Assignee: Intel Corporation
    Inventors: Chee Wai Wong, Chee Hoo Lee
  • Integrated circuit die configuration for packaging
    Patent number: 7341887
    Abstract: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package substrate in an angle with respect to a package substrate to point the corners of the die at the edges of the package substrate to reduce trace length outside the die. The center of the die may or may not coincide with the center of the substrate. In one embodiment, when compare to a centered, non-rotated die mounting position, mounting a die with corners pointing at the edges of the package substrate does not cause significant differences in substrate warpage.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: March 11, 2008
    Assignee: Intel Corporation
    Inventors: Chee Wai Wong, Chee Hoo Lee
  • Apparatuses and associated methods for improved solder joint reliability
    Patent number: 7242084
    Abstract: Apparatuses and associated methods to improve integrated circuit packaging are generally described. More specifically, apparatuses and associated methods to improve solder joint reliability are described. In this regard, according to one example embodiment, one or more strengthening pin(s) are coupled to the periphery of a package substrate, the strengthening pin(s) capable of coupling to a circuit board.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: July 10, 2007
    Assignee: Intel Corporation
    Inventors: Chee Wai Wong, Cheng Siew Tay