Abstract: The disclosure relates to power modules that include elevated inductors with capacitors disposed under the inductors. In one aspect, a power module includes a first circuit board having a first surface and a second surface opposite the first surface. One or more inductors are mounted on the first surface. Each of the one or more inductors includes a top surface and a bottom surface opposite the top surface and that faces the first surface of the first circuit board. Each inductor is elevated above the first surface of the first circuit board such that at least a portion of the bottom surface of the inductor does not contact the first surface of the first circuit board. The first circuit board includes capacitors arranged in an area below the portion of the bottom surface of the inductor that does not contact the first surface of the first circuit board.

Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

Abstract: An electromagnetic interference (“EMI”) sheet attenuator includes a planar conductive layer, a first flexible substrate and a second flexible substrate. The first flexible substrate overlies the metal backing layer and including a conductive pattern on a surface of the first flexible substrate. The second flexible substrate overlies the first flexible substrate and also includes the conductive pattern. The conductive pattern on the second flexible substrate is aligned with the conductive pattern on the first flexible substrate.

Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connector of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.

Abstract: An apparatus that includes first and second parallel converter branches, each parallel converter branch including an input node, N output nodes, a plurality of switches, a converter output node, and control logic. The control logic generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallel converter branch, the first set switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes.

Abstract: An apparatus that includes first and second parallel converter branches, each parallel converter branch including an input node, N output nodes, a plurality of switches, a converter output node, and control logic. The control logic generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallel converter branch, the first set switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes.

Abstract: An apparatus that includes first and second parallel converter branches, each parallel converter branch including an input node, N output nodes, a plurality of switches, a converter output node, and control logic. The control logic generates a first set of switch signals to control the switches of the first parallel converter branch and a second set of switch signals to control the second parallel converter branch, the first set switch signals and the second set of switch signals having respective duty cycles to cause each of the first and second parallel converter branches to output the DC output voltage on each of the N output nodes.

Abstract: A resistive element, a circuit board, and a circuit package, as well as a method of adding a resistive element to a circuit board are described. The resistive element includes a first contact point connected to a capacitor terminal, a second contact point connected to a circuit board plane, and resistive material connected to the first and second contact points. The invention may also include a circuit board with one or more resistive elements, as well as a circuit package, such as an integrated circuit or a discrete bypass capacitor, including one or more resistive elements, applied to an outside surface. The value of resistance for the resistive element can be selected by design to have a predetermined relationship with the equivalent resistance of an associated circuit board and connecting circuitry.

Abstract: Arrangements are used to supply power to a semiconductor package.

Abstract: A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.

Abstract: Arrangements are used to supply power to a semiconductor package.

Abstract: A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.

Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: Structures and methods are provided for dual referenced microstrip structures having low reference discontinuities between a microstrip trace referenced to a primary reference plane as compared to a microstrip trace referenced to a secondary reference plane.

Abstract: A power delivery system and a method for setting the parameters of the power delivery system. The effective resistance of the capacitors for each stage may be set to be substantially equal to the effective resistance of the previous stage, and the time capacitive constant of the capacitors may be set to be substantially equal to the effective inductive time constant of the previous stage.

Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: A method for fabricating a socket (300, FIG. 3) includes fabricating a conductive structure (310, FIG. 3) and embedding the conductive structure in a housing (302). The housing includes multiple openings (304) formed in the top surface. Each opening (304) provides access to conductive contacts (502, FIG. 5), which provide an electrical interface between a device that is inserted into the socket and the next level of interconnect (e.g., a PC board). In one embodiment, the embedded conductive structure (310) is electrically connected to one or more ground conducting contacts (708, FIG. 7B). The conductive structure includes column walls (312), which run in parallel with columns of contacts, and row walls (314), which run in parallel with rows of contacts and which intersect the column walls. In this manner, the conductive structure forms multiple chambers (402, FIG. 4).

Abstract: An apparatus is disclosed. The apparatus has a printed circuit board and one or several integrated circuit substrates mounted to the printed circuit board. At least one SMT component with two or more terminals is arranged between the printed circuit board and the package. In one embodiment, the SMT component replaces interconnects in the ball grid array used to mount the substrate to the printed circuit board while simultaneously connecting the SMT terminals to the substrate and the printed circuit board. The disclosed apparatus of SMT components mount results in significant reduction of inductance of the SMT connection to the substrate.