Abstract: A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SD™ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB.

Abstract: Methods of forming a semiconductor package including a single-sided substrate are disclosed. In a first embodiment of the present invention, a substrate may include a conductive layer on a top surface of the substrate, i.e., on the same side of the substrate as where the die are mounted. In a second embodiment of the present invention, a substrate may include a conductive layer on a bottom of the substrate, i.e., on the opposite side of the substrate as where the die are mounted.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: A printed circuit board is disclosed having coextensive electrical connectors and contact pad areas. Areas of the contact pads where the traces and/or vias are located may be etched away to ensure electrical isolation between the traces, vias and contact pads.

Abstract: A method of fabricating a semiconductor package, and a semiconductor package formed thereby, are disclosed. The semiconductor package may include one or more semiconductor die having die attach pads along a single side. The leadframe may include a plurality of elongated electrical leads, extending from a first side of the leadframe, beneath the die, and terminating at a second side of the leadframe adjacent to the bond pads along the single edge of the die. The leadframe may further include a dielectric spacer layer on the elongated leads. Spacing the semiconductor die from the elongated leads using the spacer layer reduces the parasitic capacitance and/or inductance of the semiconductor package formed thereby.

Abstract: A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates.

Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Abstract: A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates.

Abstract: A method of fabricating a semiconductor die and a low profile semiconductor package are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.

Abstract: A semiconductor die and a low profile semiconductor package formed therefrom are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.

Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Abstract: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.

Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Abstract: A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package. The dummy circuit pattern includes a plurality of straight line segments and a plurality of interrupt patterns to breakup one or more of the straight line segments. The interrupt patterns are provided so as to not electrically isolate areas of the dummy pattern, thus providing electrical continuity across the dummy circuit pattern.

Abstract: A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, a panel of semiconductor packages may undergo a first cutting process which cuts the curvilinear edges of the packages. Next, the partially singulated panel of packages may undergo an abrasion process for smoothing the cut curvilinear edges. The abrasion process may occur by forcing abrasive particles over the jagged side edges of a semiconductor package as a result of a pressure differential above and below the semiconductor packages. Upon completion of the abrasive process, a second cutting process may be performed which cuts along straight edges and singulates the respective packages from the panel.