Patents by Inventor Chehui Wu

Chehui Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160292812
    Abstract: A graphics processing unit (GPU) may perform three-dimensional (3D) graphics processing in accordance with a 3D graphics pipeline using a first plurality of graphics processing hardware units of the GPU. The GPU may further perform a two-dimensional (2D) graphics operation using a second plurality of graphics processing hardware units of the GPU not used in performing the 3D graphics processing and one or more graphics processing hardware units of the first plurality of graphics processing hardware units of the GPU.
    Type: Application
    Filed: September 25, 2015
    Publication date: October 6, 2016
    Inventors: Chehui Wu, Guofang Jiao, Jian Liang, Minjie Huang
  • Patent number: 8643644
    Abstract: This disclosure describes a multi-stage tessellation technique for tessellating a curve during graphics rendering. In particular, a first tessellation stage tessellates the curve into a first set of line segments that each represents a portion of the curve. A second tessellation stage further tessellates the portion of the curve represented by each of the line segments of the first set into additional line segments that more finely represent the shape of the curve. In this manner, each portion of the curve that was represented by only one line segment after the first tessellation stage is represented by more than one line segment after the second tessellation stage. In some instances, more than two tessellation stages may be performed to tessellate the curve.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: February 4, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jian Wei, Guofang Jiao, Ning Bi, Chehui Wu
  • Patent number: 8207972
    Abstract: A three-dimensional (3D) graphics pipeline which processes pixels of sub-screens in the last stage (pixel rendering) in parallel and independently. The sub-screen tasks are stored in a list in a shared memory. The shared memory is accessed by a plurality of processing threads designated for pixel rendering. The processing threads seize and lock sub-screens tasks in an orderly manner and process the tasks to create the bit map for display on a screen. The tasks are created by dividing a display area having the vertex information superimposed thereon into M×N sub-screen tasks. Based on system profiling, M and N may be varied.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: June 26, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Jian Wei, Chehui Wu, James M Brown
  • Publication number: 20090237401
    Abstract: This disclosure describes a multi-stage tessellation technique for tessellating a curve during graphics rendering. In particular, a first tessellation stage tessellates the curve into a first set of line segments that each represents a portion of the curve. A second tessellation stage further tessellates the portion of the curve represented by each of the line segments of the first set into additional line segments that more finely represent the shape of the curve. In this manner, each portion of the curve that was represented by only one line segment after the first tessellation stage is represented by more than one line segment after the second tessellation stage. In some instances, more than two tessellation stages may be performed to tessellate the curve.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 24, 2009
    Applicant: QUALCOMM Incorporated
    Inventors: Jian Wei, Guofang Jiao, Ning Bi, Chehui Wu