Abstract: A system including a central processor and a plurality of attached processors all on a single die are disclosed. Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load/store unit and logic suitable for performing a mathematical function.

Abstract: A system including a central processor and a plurality of attached processors all on a single die are disclosed Each of the attached processors is preferably functionally equivalent to each of the other attached processors. The system further includes at least one redundant processor that is connectable to the central processor. The redundant processor may be substantially equivalent to each of the attached processors. Upon detecting a failure in one of the attached processors, the system is configured to disable the non-functional processor and enable the redundant processor. The attached processors may be connected to a memory interface unit via a parallel bus or a pipelined bus in which each attached processor is connected to a stage of the pipelined bus. The attached processors may each include a load store unit and logic suitable for performing a mathematical function.

Abstract: A reprogrammable logic fuse (RLF) based on a 6 device standard Static Random Access Memory (SRAM) cell includes a storage element comprised of four cross coupled FETs. A fifth FET is mounted in a transmission gate configuration between the bit line and a first common node of the storage element. Its gate electrode is connected to the word line. This FET is used to write the appropriate control data in the storage element for bit personality store. A sixth FET is also mounted in a transmission gate configuration between the second common node of the storage element and an output line. Its gate electrode is connected to the input line. This sixth FET ensures that a logical function, e.g. AND/NAND is achieved between the signals available at the second common node and on the input line. Other configurations of said sixth FET are allowed. These reprogrammable logic fuses may be disposed in matrixes to constitute reloadable logic arrays and Reloadable PLAs (RPLAs).

Abstract: In combination with an electronic memory of the type having a plurality of memory cells (CA, . . . CN) connected between two bit lines (BLT, BLC) having inherent bit line capacitances (C1, C2), there is disclosed an improved sense amplifier (15) comprised of two stages. A first stage (16) includes a first clocked latch (5) having an enable device (T5), gated by a first control signal (SSA) and bit switches (T6, T7) connected between the common nodes (6, 7) of said first clocked latch and said bit lines, and gated by a bit switch control signal (BS) to provide an output signal on first data lines (DLT, DLC). A second stage (17) includes a second clocked latch (20) having an enable device (T24) gated by a second signal (SL) and data switches (T28, T29) connected between second data lines (DT, DC) at the same potential as data output nodes (21, 22) of said second clocked latch and said first data lines (DLT, DLC).

Abstract: A semiconductor memory device including a pair of bit lines (BL, BL) having relatively high stray capacitances (C1, C2), a word line (WL), and a memory cell (MC1) connected to the bit lines and word line for selection by an address signal, and a restore circuit comprising a coupling/equalizing circuit (12) controlled by a BLR clock and a reference voltage generator (51) for quickly restoring the bit lines. The reference voltage generator (51) comprises both static and dynamic current sources. The static current source consists of a small N MOS transistor (N52) operating as a resistor load, while the dynamic current source consists of at least one small P MOS transistor (P'53, . . . ), connected in parallel with the N MOS transistor, and gated with a clock (BCC', . . . ) derived from the BLR clock, so that the P MOS transistor is turned ON during the restore time. An additional N device (N54) may be inserted between the reference line (RL) and ground (GND).