Patents by Inventor Chel-jong Choi
Chel-jong Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7981735Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.Type: GrantFiled: May 4, 2009Date of Patent: July 19, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Yark Yeon Kim, Seong Jae Lee, Moon Gyu Jang, Chel Jong Choi, Myung Sim Jun, Byoung Chul Park
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Publication number: 20110068326Abstract: A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.Type: ApplicationFiled: November 30, 2010Publication date: March 24, 2011Inventors: Moon-Gyu Jang, Yark-Yeon Kim, Chel-Jong Choi, Myung-Sim Jun, Tae-Youb Kim, Seong-Jae Lee
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Patent number: 7863121Abstract: A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.Type: GrantFiled: May 8, 2007Date of Patent: January 4, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Moon-Gyu Jang, Yark-Yeon Kim, Chel-Jong Choi, Myung-Sim Jun, Tae-Youb Kim, Seong-Jae Lee
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Patent number: 7745316Abstract: Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.Type: GrantFiled: October 31, 2007Date of Patent: June 29, 2010Assignee: Electronics and Telecommunications Research InstituteInventors: Yark-Yeon Kim, Seong-Jae Lee, Moon-Gyu Jang, Tae-Youb Kim, Chel-Jong Choi, Myung-Sim Jun, Byoung-Chul Park
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Patent number: 7713826Abstract: Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.Type: GrantFiled: March 11, 2008Date of Patent: May 11, 2010Assignee: Electronics and Telecommunications Research InstituteInventors: Chel Jong Choi, Moon Gyu Jang, Yark Yeon Kim, Myung Sim Jun, Tae Youb Kim
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Patent number: 7605068Abstract: Provided is a semiconductor device and a manufacturing method thereof. The method includes the steps of: forming a thin film transistor including a substrate having a semiconductor layer and silicon, a gate insulation layer formed on the semiconductor layer, a gate electrode formed on the gate insulation layer, and source and drain regions formed in the semiconductor layer; forming a first metal layer on the substrate having the semiconductor layer and the gate electrode; forming a second metal layer on the first metal layer; forming a third metal layer on the second metal layer; forming a nitride layer on the third metal layer; and annealing the substrate having the nitride layer, and forming a silicide layer on the gate electrode and the source and drain regions.Type: GrantFiled: January 31, 2006Date of Patent: October 20, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Chel Jong Choi, Yong Jin Kim, Hi Deok Lee
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Publication number: 20090215232Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.Type: ApplicationFiled: May 4, 2009Publication date: August 27, 2009Inventors: Yark Yeon KIM, Seong Jae LEE, Moon Gyu JANG, Chel Jong CHOI, Myung Sim JUN, Byoung Chul PARK
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Patent number: 7569846Abstract: A phase-change random access memory (PRAM) device including a plurality of nanowires and a method of manufacturing the same include: a lower structure including a plurality of contact plugs; the nanowires extending into the contact plugs from surfaces defining a respective terminal end of the contact plugs; and a phase-change layer formed on top of the nanowires. Therefore, a reset or a set current consumed by the PRAM device is significantly reduced.Type: GrantFiled: May 8, 2006Date of Patent: August 4, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Chel-jong Choi, Jong-bong Park, Tae-gyu Kim, Dong-woo Lee
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Patent number: 7545000Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.Type: GrantFiled: July 13, 2006Date of Patent: June 9, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Yark Yeon Kim, Seong Jae Lee, Moon Gyu Jang, Chel Jong Choi, Myung Sim Jun, Byoung Chul Park
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Publication number: 20080299736Abstract: Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.Type: ApplicationFiled: March 11, 2008Publication date: December 4, 2008Applicant: Electronics and Telecommunications research InstituteInventors: Chel Jong Choi, Moon Gyu Jang, Yark Yeon Kim, Myung Sim Jun, Tae Youb Kim
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Patent number: 7449402Abstract: Provided is a method of fabricating a semiconductor device, the method including: forming an insulating layer on a single crystal substrate; etching the insulating layer in a predetermined pattern to expose the surface of the single crystal substrate; depositing an amorphous material on the insulating layer and the exposed surface of the single crystal substrate; and completely melting the amorphous material on the single crystal substrate and the insulating layer using laser annealing and crystallizing the melted amorphous material. The semiconductor device has a single crystalline silicon gate on the insulating layer.Type: GrantFiled: January 23, 2006Date of Patent: November 11, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Soo-bong Heo, Chel-jong Choi
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Publication number: 20080128760Abstract: Provided is a Schottky barrier nanowire field effect transistor, which has source/drain electrodes formed of metal silicide and a channel formed of a nanowire, and a method for fabricating the same. The Schottky barrier nanowire field effect transistor includes: a channel suspended over a substrate and including a nanowire; metal silicide source/drain electrodes electrically connected to both ends of the channel over the substrate; a gate electrode disposed to surround the channel; and a gate insulation layer disposed between the channel and the gate electrode.Type: ApplicationFiled: November 30, 2007Publication date: June 5, 2008Applicant: Electronics and Telecommunications Research InstituteInventors: Myungsim Jun, Moon-Gyu Jang, Yark-Yeon Kim, Chel-Jong Choi, Taeyoub Kim, Seongjae Lee
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Publication number: 20080128786Abstract: Provided are a high density semiconductor memory device capable of precisely reading data by suppressing the occurrence of a leakage current due to the high-integration of the semiconductor memory device, and a method for manufacturing the semiconductor memory device. The high density semiconductor memory device includes: source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; and a floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots. The nanodots may be formed of a silicon compound or any material that can be charged.Type: ApplicationFiled: December 4, 2007Publication date: June 5, 2008Applicant: Electronics and Telecommunications Research InstituteInventors: Taeyoub KIM, Myungsim JUN, Yark-Yeon KIM, Moon-Gyu JANG, Chel-Jong CHOI, Seong-Jae LEE, Byoungchul PARK
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Publication number: 20080132049Abstract: Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.Type: ApplicationFiled: October 31, 2007Publication date: June 5, 2008Applicant: Electronics and Telecommunications Research InstituteInventors: Yark-Yeon KIM, Seong-Jae Lee, Moon-Gyu Jang, Tae-Youb Kim, Chel-Jong Choi, Myung-Sim Jun, Byoung-Chul Park
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Publication number: 20080121868Abstract: A Schottky barrier tunnel transistor includes a gate electrode, and source and drain regions. The gate electrode is formed over a channel region of a substrate to form a Schottky junction with the substrate. The source and drain regions are formed in the substrate exposed on both sides of the gate electrode.Type: ApplicationFiled: May 8, 2007Publication date: May 29, 2008Inventors: Moon-Gyu Jang, Yark-Yeon Kim, Chel-Jong Choi, Myung-Sim Jun, Tae-Youb Kim, Seong-Jae Lee
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Publication number: 20080124854Abstract: A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, forming a conductive compound containing layer over the gate insulation layer, etching the conductive compound containing layer and the gate insulation layer to form a gate structure, forming a metal layer over the resultant structure obtained after the etching, and letting the metal layer to react with silicon from the substrate to form source and drain regions comprising a metal silicide layer over the substrate exposed on both sides of the gate structure, wherein the conductive compound containing layer does not react with the metal layer.Type: ApplicationFiled: May 7, 2007Publication date: May 29, 2008Inventors: Chel-Jong CHOI, Moon-Gyu JANG, Yark-Yeon KIM, Tae-Youb KIM, Myung-Sim JUN, Seong-Jae LEE
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Patent number: 7279422Abstract: Provided is a semiconductor device having a suicide thin film with thermal stability and a method of manufacturing the same. The semiconductor device includes a silicon substrate containing Si a gate oxide film formed on the silicon substrate, a gate electrode containing Si formed on the gate oxide film, a spacer formed on side walls of the gate oxide film and the gate electrode, a LDD region formed in the silicon substrate under the spacer, a source/drain region formed in the silicon substrate, a NiSi thin film formed on the source/drain region and the gate electrode by reacting a Ni film with the source/drain region and the gate electrode; and a nitride film formed on the NiSi thin film formed by surface treating the nickel film using Ar plasma and reacting the Ni film with nitrogen. The, a semiconductor device having the NiSi thin film has a low sheet resistance and high thermal stability can be obtained.Type: GrantFiled: August 11, 2004Date of Patent: October 9, 2007Assignee: Samsung Electronics Co., Ltd.Inventor: Chel-jong Choi
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Publication number: 20070012986Abstract: a phase-change random access memory (PRAM) device including a plurality of nanowires and a method of manufacturing the same include: a lower structure including a plurality of contact plugs; the nanowires extending into the contact plugs from surfaces defining a respective terminal end of the contact plugs; and a phase-change layer formed on top of the nanowires. Therefore, a reset or a set current consumed by the PRAM device is significantly reduced.Type: ApplicationFiled: May 8, 2006Publication date: January 18, 2007Inventors: Chel-jong Choi, Jong-bong Park, Tae-gyu Kim, Dong-woo Lee
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Patent number: 7153770Abstract: A semiconductor device comprising a metal silicide film with uniform surface morphology and interface morphology and a method of manufacturing the same are provided. The metal silicide film of the semiconductor device exhibits low sheet resistance and excellent thermal stability. Therefore, by using the semiconductor device fabrication method, high performance, high quality semiconductor devices can be manufactured.Type: GrantFiled: December 29, 2003Date of Patent: December 26, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Chel-jong Choi
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Publication number: 20060286787Abstract: A semiconductor device comprising a metal silicide film with uniform surface morphology and interface morphology and a method of manufacturing the same are provided. The metal silicide film of the semiconductor device exhibits low sheet resistance and excellent thermal stability. Therefore, by using the semiconductor device fabrication method, high performance, high quality semiconductor devices can be manufactured.Type: ApplicationFiled: August 24, 2006Publication date: December 21, 2006Applicant: Samsung Electronics Co., Ltd.Inventor: Chel-Jong Choi