Abstract: A warning device that combines a radar module with electronic control technology can accurately detect the velocity and the distance of an object around the warning device and provide dynamic warning (e.g., flashing or buzzing). The radar module, installed in an electronic component box, maintains a given distance from the ground to avoid echo interference from the ground, thereby reducing the noise of the collected point-cloud data. A controller extracts the relative velocity and the location of the object from the point-cloud data, selects dynamically approaching points to determine the relative distance and the direction of the object, and dynamically adjusts the flashing frequency of a warning lamp or turns on a buzzer based on the distance of the object relative to the radar module.

Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.

Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.

Abstract: A method includes forming a channel region over a substrate; forming an isolation feature over the substrate and alongside the channel region; forming a source/drain feature interfacing a sidewall of the channel region; forming a gate structure over the channel region, wherein the gate structure comprises at a dielectric layer and a metal layer; etching the gate structure to form an opening that divides the gate structure into two separate segments; forming a first spacer layer along a sidewall of the opening; forming a second spacer layer over the first spacer layer; removing the first spacer layer such that an air spacer is formed between the second spacer layer and one of the separate segments of the gate structure; filling a dielectric material into the opening and over the second spacer layer, with the air spacer being maintained between the second spacer layer and the gate structure.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction; a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction; a first isolation structure extending into the interlayer dielectric, disposed between the first and second source/drain structures, and disposed next to a gate structure along the first direction; and a second isolation structure below the first and second conduction channels. The second isolation structure includes a shallow trench isolation structure.

Abstract: A semiconductor structure includes a gate, a self-aligned contact (SAC) layer that is disposed on the gate and that has a seam at a top surface of the SAC layer, a gate spacer that is formed on a sidewall of the gate, and a metal contact that is disposed adjacent to the gate spacer and that is spaced apart from the gate by the gate spacer. The SAC layer includes a filler that seals the seam in the SAC layer, and a top surface of the filler is coplanar with a top surface of the gate spacer and a top surface of the metal contact.

Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.

Abstract: A method is provided for sealing a seam in a self-aligned contact (SAC) layer that is disposed on a gate of a semiconductor structure. The method includes depositing a filler in the seam to seal the seam.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.

Abstract: A rotation locking system of a motor of a fan is provided. A closed-loop control circuit outputs an initial duty cycle signal according to a current rotational speed and a target rotational speed. A driver circuit outputs a driving signal to the motor to drive the motor to rotate according to the initial duty cycle signal. A lookup table arithmetic circuit looks up, from a lookup table, two reference duty cycles correspond to two reference rotational speeds that are respectively equal to the current rotational speed and the target rotational speed. The lookup table arithmetic circuit calculates a difference between the two reference duty cycles. A speed feedback control circuit compensates the initial duty cycle signal according to the difference to output a final duty cycle signal to the driver circuit. The driver circuit drives the motor to rotate according to the final duty cycle signal.

Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.

Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.

Abstract: A semiconductor device includes a first source/drain structure coupled to an end of a first conduction channel that extends along a first direction. The semiconductor device includes a second source/drain structure coupled to an end of a second conduction channel that extends along the first direction. The semiconductor device includes a first interconnect structure extending through an interlayer dielectric and electrically coupled to the first source/drain structure. The semiconductor device includes a second interconnect structure extending through the interlayer dielectric and electrically coupled to the second source/drain structure. The semiconductor device includes a first isolation structure disposed between the first and second source/drain structures and extending into the interlayer dielectric.

Abstract: A package substrate is adapted to a ball grid array package. The substrate includes two substrate contacts, two solder ball pads, two via holes and two signal lines. A connection line of the two substrate contacts is substantially perpendicular to a connection line of the two solder ball pads. The two substrate contacts are respectively connected to the two via holes by the two signal lines. Each signal line includes a circuit trace section, an approaching section and a bifurcating section connected in sequence. The two circuit trace sections of each signal line are substantially arranged in parallel. The two approaching sections are substantially arranged in parallel and substantially symmetrical about the connection line of the solder ball pads. The two bifurcating sections are substantially symmetrical about the pad connection line and respectively electrically connected to the two via holes.

Abstract: A rotation locking system of a motor of a fan is provided. A closed-loop control circuit outputs an initial duty cycle signal according to a current rotational speed and a target rotational speed. A driver circuit outputs a driving signal to the motor to drive the motor to rotate according to the initial duty cycle signal. A lookup table arithmetic circuit looks up, from a lookup table, two reference duty cycles correspond to two reference rotational speeds that are respectively equal to the current rotational speed and the target rotational speed. The lookup table arithmetic circuit calculates a difference between the two reference duty cycles. A speed feedback control circuit compensates the initial duty cycle signal according to the difference to output a final duty cycle signal to the driver circuit. The driver circuit drives the motor to rotate according to the final duty cycle signal.

Abstract: A method is provided for sealing a seam in a self-aligned contact (SAC) layer that is disposed on a gate of a semiconductor structure. The method includes depositing a filler in the seam to seal the seam.

Abstract: A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a shallow trench isolation (STI) structure, an air spacer, and a gate structure. The semiconductor fin extends upwardly from the substrate. The STI structure laterally surrounds a lower portion of the semiconductor fin. The air spacer is interposed the STI structure and the semiconductor fin. The gate structure extends across the semiconductor fin.